//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This tablegen backend is responsible for emitting a description of the target
#include "InstrInfoEmitter.h"
#include "CodeGenTarget.h"
#include "Record.h"
+#include <algorithm>
using namespace llvm;
// runEnums - Print out enum values for all of the instructions.
// We must emit the PHI opcode first...
Record *InstrInfo = Target.getInstructionSet();
- Record *PHI = InstrInfo->getValueAsDef("PHIInst");
std::string Namespace = Target.inst_begin()->second.Namespace;
OS << "namespace " << Namespace << " {\n";
OS << " enum {\n";
- OS << " " << PHI->getName() << ", \t// 0 (fixed for all targets)\n";
-
- // Print out the rest of the instructions now.
- unsigned i = 0;
- for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
- E = Target.inst_end(); II != E; ++II)
- if (II->second.TheDef != PHI)
- OS << " " << II->first << ", \t// " << ++i << "\n";
-
+ std::vector<const CodeGenInstruction*> NumberedInstructions;
+ Target.getInstructionsByEnumValue(NumberedInstructions);
+
+ for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
+ OS << " " << NumberedInstructions[i]->TheDef->getName()
+ << ", \t// " << i << "\n";
+ }
+ OS << " INSTRUCTION_LIST_END\n";
OS << " };\n";
if (!Namespace.empty())
OS << "}\n";
OS << "} // End llvm namespace \n";
}
-void InstrInfoEmitter::printDefList(ListInit *LI, const std::string &Name,
- std::ostream &OS) const {
- OS << "static const unsigned " << Name << "[] = { ";
- for (unsigned j = 0, e = LI->getSize(); j != e; ++j)
- if (DefInit *DI = dynamic_cast<DefInit*>(LI->getElement(j)))
- OS << getQualifiedName(DI->getDef()) << ", ";
- else
- throw "Illegal value in '" + Name + "' list!";
+void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses,
+ unsigned Num, std::ostream &OS) const {
+ OS << "static const unsigned ImplicitList" << Num << "[] = { ";
+ for (unsigned i = 0, e = Uses.size(); i != e; ++i)
+ OS << getQualifiedName(Uses[i]) << ", ";
OS << "0 };\n";
}
+static std::vector<Record*> GetOperandInfo(const CodeGenInstruction &Inst) {
+ std::vector<Record*> Result;
+ if (Inst.hasVariableNumberOfOperands)
+ return Result; // No info for variable operand instrs.
+
+ for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
+ if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass")) {
+ Result.push_back(Inst.OperandList[i].Rec);
+ } else {
+ // This might be a multiple operand thing.
+ // Targets like X86 have registers in their multi-operand operands.
+ DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
+ unsigned NumDefs = MIOI->getNumArgs();
+ for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
+ if (NumDefs <= j) {
+ Result.push_back(0);
+ } else {
+ DefInit *Def = dynamic_cast<DefInit*>(MIOI->getArg(j));
+ Result.push_back(Def ? Def->getDef() : 0);
+ }
+ }
+ }
+ }
+ return Result;
+}
+
// run - Emit the main instruction description records for the target...
void InstrInfoEmitter::run(std::ostream &OS) {
+ GatherItinClasses();
+
EmitSourceFileHeader("Target Instruction Descriptors", OS);
OS << "namespace llvm {\n\n";
Record *PHI = InstrInfo->getValueAsDef("PHIInst");
// Emit empty implicit uses and defs lists
- OS << "static const unsigned EmptyImpUses[] = { 0 };\n"
- << "static const unsigned EmptyImpDefs[] = { 0 };\n";
+ OS << "static const unsigned EmptyImpList[] = { 0 };\n";
- // Emit all of the instruction's implicit uses and defs...
+ // Keep track of all of the def lists we have emitted already.
+ std::map<std::vector<Record*>, unsigned> EmittedLists;
+ unsigned ListNumber = 0;
+
+ // Emit all of the instruction's implicit uses and defs.
for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
E = Target.inst_end(); II != E; ++II) {
Record *Inst = II->second.TheDef;
- ListInit *LI = Inst->getValueAsListInit("Uses");
- if (LI->getSize()) printDefList(LI, Inst->getName()+"ImpUses", OS);
- LI = Inst->getValueAsListInit("Defs");
- if (LI->getSize()) printDefList(LI, Inst->getName()+"ImpDefs", OS);
+ std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
+ if (!Uses.empty()) {
+ unsigned &IL = EmittedLists[Uses];
+ if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
+ }
+ std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
+ if (!Defs.empty()) {
+ unsigned &IL = EmittedLists[Defs];
+ if (!IL) printDefList(Defs, IL = ++ListNumber, OS);
+ }
}
+ std::map<std::vector<Record*>, unsigned> OperandInfosEmitted;
+ unsigned OperandListNum = 0;
+ OperandInfosEmitted[std::vector<Record*>()] = ++OperandListNum;
+
+ // Emit all of the operand info records.
+ OS << "\n";
+ for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
+ E = Target.inst_end(); II != E; ++II) {
+ std::vector<Record*> OperandInfo = GetOperandInfo(II->second);
+ unsigned &N = OperandInfosEmitted[OperandInfo];
+ if (N == 0) {
+ N = ++OperandListNum;
+ OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
+ for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) {
+ Record *RC = OperandInfo[i];
+ // FIXME: We only care about register operands for now.
+ if (RC && RC->isSubClassOf("RegisterClass")) {
+ OS << "{ &" << getQualifiedName(RC) << "RegClass }, ";
+ } else {
+ OS << "{ 0 }, ";
+ }
+ }
+ OS << "};\n";
+ }
+ }
+
+ // Emit all of the TargetInstrDescriptor records.
+ //
OS << "\nstatic const TargetInstrDescriptor " << TargetName
<< "Insts[] = {\n";
- emitRecord(Target.getPHIInstruction(), 0, InstrInfo, OS);
+ emitRecord(Target.getPHIInstruction(), 0, InstrInfo, EmittedLists,
+ OperandInfosEmitted, OS);
unsigned i = 0;
for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
E = Target.inst_end(); II != E; ++II)
if (II->second.TheDef != PHI)
- emitRecord(II->second, ++i, InstrInfo, OS);
+ emitRecord(II->second, ++i, InstrInfo, EmittedLists,
+ OperandInfosEmitted, OS);
OS << "};\n";
OS << "} // End llvm namespace \n";
}
void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
- Record *InstrInfo, std::ostream &OS) {
+ Record *InstrInfo,
+ std::map<std::vector<Record*>, unsigned> &EmittedLists,
+ std::map<std::vector<Record*>, unsigned> &OpInfo,
+ std::ostream &OS) {
+ int NumOperands;
+ if (Inst.hasVariableNumberOfOperands)
+ NumOperands = -1;
+ else if (!Inst.OperandList.empty())
+ // Each logical operand can be multiple MI operands.
+ NumOperands = Inst.OperandList.back().MIOperandNo +
+ Inst.OperandList.back().MINumOperands;
+ else
+ NumOperands = 0;
+
OS << " { \"";
if (Inst.Name.empty())
OS << Inst.TheDef->getName();
else
OS << Inst.Name;
- OS << "\",\t-1, -1, 0, false, 0, 0, 0, 0";
+
+ unsigned ItinClass = !IsItineraries ? 0 :
+ ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName());
+
+ OS << "\",\t" << NumOperands << ", -1, 0, false, 0, 0, "
+ << ItinClass
+ << ", 0";
// Emit all of the target indepedent flags...
if (Inst.isReturn) OS << "|M_RET_FLAG";
if (Inst.isBarrier) OS << "|M_BARRIER_FLAG";
if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
if (Inst.isCall) OS << "|M_CALL_FLAG";
+ if (Inst.isLoad) OS << "|M_LOAD_FLAG";
+ if (Inst.isStore) OS << "|M_STORE_FLAG";
if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG";
+ if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
+ if (Inst.isCommutable) OS << "|M_COMMUTABLE";
if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
+ if (Inst.usesCustomDAGSchedInserter)
+ OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
OS << ", 0";
// Emit all of the target-specific flags...
OS << ", ";
// Emit the implicit uses and defs lists...
- LI = Inst.TheDef->getValueAsListInit("Uses");
- if (!LI->getSize())
- OS << "EmptyImpUses, ";
- else
- OS << Inst.TheDef->getName() << "ImpUses, ";
-
- LI = Inst.TheDef->getValueAsListInit("Defs");
- if (!LI->getSize())
- OS << "EmptyImpDefs ";
- else
- OS << Inst.TheDef->getName() << "ImpDefs ";
+ std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
+ if (UseList.empty())
+ OS << "EmptyImpList, ";
+ else
+ OS << "ImplicitList" << EmittedLists[UseList] << ", ";
+ std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
+ if (DefList.empty())
+ OS << "EmptyImpList, ";
+ else
+ OS << "ImplicitList" << EmittedLists[DefList] << ", ";
+
+ // Emit the operand info.
+ std::vector<Record*> OperandInfo = GetOperandInfo(Inst);
+ if (OperandInfo.empty())
+ OS << "0";
+ else
+ OS << "OperandInfo" << OpInfo[OperandInfo];
+
OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
}
+struct LessRecord {
+ bool operator()(const Record *Rec1, const Record *Rec2) const {
+ return Rec1->getName() < Rec2->getName();
+ }
+};
+void InstrInfoEmitter::GatherItinClasses() {
+ std::vector<Record*> DefList =
+ Records.getAllDerivedDefinitions("InstrItinClass");
+ IsItineraries = !DefList.empty();
+
+ if (!IsItineraries) return;
+
+ std::sort(DefList.begin(), DefList.end(), LessRecord());
+
+ for (unsigned i = 0, N = DefList.size(); i < N; i++) {
+ Record *Def = DefList[i];
+ ItinClassMap[Def->getName()] = i;
+ }
+}
+
+unsigned InstrInfoEmitter::ItinClassNumber(std::string ItinName) {
+ return ItinClassMap[ItinName];
+}
+
void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
IntInit *ShiftInt, std::ostream &OS) {
if (Val == 0 || ShiftInt == 0)
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