//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
#include "InstrInfoEmitter.h"
#include "CodeGenTarget.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "Record.h"
+#include "llvm/ADT/StringExtras.h"
#include <algorithm>
using namespace llvm;
-// runEnums - Print out enum values for all of the instructions.
-void InstrInfoEmitter::runEnums(std::ostream &OS) {
- EmitSourceFileHeader("Target Instruction Enum Values", OS);
- OS << "namespace llvm {\n\n";
+static void PrintDefList(const std::vector<Record*> &Uses,
+ unsigned Num, raw_ostream &OS) {
+ OS << "static const unsigned ImplicitList" << Num << "[] = { ";
+ for (unsigned i = 0, e = Uses.size(); i != e; ++i)
+ OS << getQualifiedName(Uses[i]) << ", ";
+ OS << "0 };\n";
+}
- CodeGenTarget Target;
+static void PrintBarriers(std::vector<Record*> &Barriers,
+ unsigned Num, raw_ostream &OS) {
+ OS << "static const TargetRegisterClass* Barriers" << Num << "[] = { ";
+ for (unsigned i = 0, e = Barriers.size(); i != e; ++i)
+ OS << "&" << getQualifiedName(Barriers[i]) << "RegClass, ";
+ OS << "NULL };\n";
+}
- // We must emit the PHI opcode first...
- std::string Namespace;
- for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
- E = Target.inst_end(); II != E; ++II) {
- if (II->second.Namespace != "TargetInstrInfo") {
- Namespace = II->second.Namespace;
- break;
- }
- }
-
- if (Namespace.empty()) {
- cerr << "No instructions defined!\n";
- exit(1);
- }
+//===----------------------------------------------------------------------===//
+// Instruction Itinerary Information.
+//===----------------------------------------------------------------------===//
- std::vector<const CodeGenInstruction*> NumberedInstructions;
- Target.getInstructionsByEnumValue(NumberedInstructions);
+void InstrInfoEmitter::GatherItinClasses() {
+ std::vector<Record*> DefList =
+ Records.getAllDerivedDefinitions("InstrItinClass");
+ std::sort(DefList.begin(), DefList.end(), LessRecord());
+
+ for (unsigned i = 0, N = DefList.size(); i < N; i++)
+ ItinClassMap[DefList[i]->getName()] = i;
+}
- OS << "namespace " << Namespace << " {\n";
- OS << " enum {\n";
- for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
- OS << " " << NumberedInstructions[i]->TheDef->getName()
- << "\t= " << i << ",\n";
- }
- OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
- OS << " };\n}\n";
- OS << "} // End llvm namespace \n";
+unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
+ return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()];
}
-void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses,
- unsigned Num, std::ostream &OS) const {
- OS << "static const unsigned ImplicitList" << Num << "[] = { ";
- for (unsigned i = 0, e = Uses.size(); i != e; ++i)
- OS << getQualifiedName(Uses[i]) << ", ";
- OS << "0 };\n";
-}
+//===----------------------------------------------------------------------===//
+// Operand Info Emission.
+//===----------------------------------------------------------------------===//
std::vector<std::string>
InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
if (OpR->isSubClassOf("RegisterClass"))
Res += getQualifiedName(OpR) + "RegClassID, ";
+ else if (OpR->isSubClassOf("PointerLikeRegClass"))
+ Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
else
Res += "0, ";
+
// Fill in applicable flags.
Res += "0";
// Ptr value whose register class is resolved via callback.
- if (OpR->getName() == "ptr_rc")
- Res += "|M_LOOK_UP_PTR_REG_CLASS";
+ if (OpR->isSubClassOf("PointerLikeRegClass"))
+ Res += "|(1<<TOI::LookupPtrRegClass)";
// Predicate operands. Check to see if the original unexpanded operand
// was of type PredicateOperand.
if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
- Res += "|M_PREDICATE_OPERAND";
+ Res += "|(1<<TOI::Predicate)";
// Optional def operands. Check to see if the original unexpanded operand
// was of type OptionalDefOperand.
if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand"))
- Res += "|M_OPTIONAL_DEF_OPERAND";
+ Res += "|(1<<TOI::OptionalDef)";
// Fill in constraint info.
- Res += ", " + Inst.OperandList[i].Constraints[j];
+ Res += ", ";
+
+ const CodeGenInstruction::ConstraintInfo &Constraint =
+ Inst.OperandList[i].Constraints[j];
+ if (Constraint.isNone())
+ Res += "0";
+ else if (Constraint.isEarlyClobber())
+ Res += "(1 << TOI::EARLY_CLOBBER)";
+ else {
+ assert(Constraint.isTied());
+ Res += "((" + utostr(Constraint.getTiedOperand()) +
+ " << 16) | (1 << TOI::TIED_TO))";
+ }
+
Result.push_back(Res);
}
}
return Result;
}
+void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
+ OperandInfoMapTy &OperandInfoIDs) {
+ // ID #0 is for no operand info.
+ unsigned OperandListNum = 0;
+ OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
+
+ OS << "\n";
+ const CodeGenTarget &Target = CDP.getTargetInfo();
+ for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
+ E = Target.inst_end(); II != E; ++II) {
+ std::vector<std::string> OperandInfo = GetOperandInfo(**II);
+ unsigned &N = OperandInfoIDs[OperandInfo];
+ if (N != 0) continue;
+
+ N = ++OperandListNum;
+ OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
+ for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
+ OS << "{ " << OperandInfo[i] << " }, ";
+ OS << "};\n";
+ }
+}
+
+void InstrInfoEmitter::DetectRegisterClassBarriers(std::vector<Record*> &Defs,
+ const std::vector<CodeGenRegisterClass> &RCs,
+ std::vector<Record*> &Barriers) {
+ std::set<Record*> DefSet;
+ unsigned NumDefs = Defs.size();
+ for (unsigned i = 0; i < NumDefs; ++i)
+ DefSet.insert(Defs[i]);
+
+ for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
+ const CodeGenRegisterClass &RC = RCs[i];
+ unsigned NumRegs = RC.Elements.size();
+ if (NumRegs > NumDefs)
+ continue; // Can't possibly clobber this RC.
+
+ bool Clobber = true;
+ for (unsigned j = 0; j < NumRegs; ++j) {
+ Record *Reg = RC.Elements[j];
+ if (!DefSet.count(Reg)) {
+ Clobber = false;
+ break;
+ }
+ }
+ if (Clobber)
+ Barriers.push_back(RC.TheDef);
+ }
+}
+
+//===----------------------------------------------------------------------===//
+// Main Output.
+//===----------------------------------------------------------------------===//
// run - Emit the main instruction description records for the target...
-void InstrInfoEmitter::run(std::ostream &OS) {
+void InstrInfoEmitter::run(raw_ostream &OS) {
GatherItinClasses();
EmitSourceFileHeader("Target Instruction Descriptors", OS);
OS << "namespace llvm {\n\n";
- CodeGenTarget Target;
+ CodeGenTarget &Target = CDP.getTargetInfo();
const std::string &TargetName = Target.getName();
Record *InstrInfo = Target.getInstructionSet();
+ const std::vector<CodeGenRegisterClass> &RCs = Target.getRegisterClasses();
// Keep track of all of the def lists we have emitted already.
std::map<std::vector<Record*>, unsigned> EmittedLists;
unsigned ListNumber = 0;
+ std::map<std::vector<Record*>, unsigned> EmittedBarriers;
+ unsigned BarrierNumber = 0;
+ std::map<Record*, unsigned> BarriersMap;
// Emit all of the instruction's implicit uses and defs.
for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
E = Target.inst_end(); II != E; ++II) {
- Record *Inst = II->second.TheDef;
+ Record *Inst = (*II)->TheDef;
std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
if (!Uses.empty()) {
unsigned &IL = EmittedLists[Uses];
- if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
+ if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
}
std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
if (!Defs.empty()) {
+ std::vector<Record*> RCBarriers;
+ DetectRegisterClassBarriers(Defs, RCs, RCBarriers);
+ if (!RCBarriers.empty()) {
+ unsigned &IB = EmittedBarriers[RCBarriers];
+ if (!IB) PrintBarriers(RCBarriers, IB = ++BarrierNumber, OS);
+ BarriersMap.insert(std::make_pair(Inst, IB));
+ }
+
unsigned &IL = EmittedLists[Defs];
- if (!IL) printDefList(Defs, IL = ++ListNumber, OS);
+ if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
}
}
- std::map<std::vector<std::string>, unsigned> OperandInfosEmitted;
- unsigned OperandListNum = 0;
- OperandInfosEmitted[std::vector<std::string>()] = ++OperandListNum;
+ OperandInfoMapTy OperandInfoIDs;
// Emit all of the operand info records.
- OS << "\n";
- for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
- E = Target.inst_end(); II != E; ++II) {
- std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
- unsigned &N = OperandInfosEmitted[OperandInfo];
- if (N == 0) {
- N = ++OperandListNum;
- OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
- for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
- OS << "{ " << OperandInfo[i] << " }, ";
- OS << "};\n";
- }
- }
+ EmitOperandInfo(OS, OperandInfoIDs);
- // Emit all of the TargetInstrDescriptor records in their ENUM ordering.
+ // Emit all of the TargetInstrDesc records in their ENUM ordering.
//
- OS << "\nstatic const TargetInstrDescriptor " << TargetName
+ OS << "\nstatic const TargetInstrDesc " << TargetName
<< "Insts[] = {\n";
- std::vector<const CodeGenInstruction*> NumberedInstructions;
- Target.getInstructionsByEnumValue(NumberedInstructions);
+ const std::vector<const CodeGenInstruction*> &NumberedInstructions =
+ Target.getInstructionsByEnumValue();
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
- OperandInfosEmitted, OS);
+ BarriersMap, OperandInfoIDs, OS);
OS << "};\n";
OS << "} // End llvm namespace \n";
}
void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
Record *InstrInfo,
std::map<std::vector<Record*>, unsigned> &EmittedLists,
- std::map<std::vector<std::string>, unsigned> &OpInfo,
- std::ostream &OS) {
- int MinOperands;
+ std::map<Record*, unsigned> &BarriersMap,
+ const OperandInfoMapTy &OpInfo,
+ raw_ostream &OS) {
+ int MinOperands = 0;
if (!Inst.OperandList.empty())
// Each logical operand can be multiple MI operands.
MinOperands = Inst.OperandList.back().MIOperandNo +
Inst.OperandList.back().MINumOperands;
- else
- MinOperands = 0;
-
+
OS << " { ";
OS << Num << ",\t" << MinOperands << ",\t"
- << Inst.NumDefs << ",\t\"";
-
- if (Inst.Name.empty())
- OS << Inst.TheDef->getName();
- else
- OS << Inst.Name;
-
- unsigned ItinClass = !IsItineraries ? 0 :
- ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName());
-
- OS << "\",\t" << ItinClass << ", 0";
-
- // Try to determine (from the pattern), if the instruction is a store.
- bool isStore = false;
- if (dynamic_cast<ListInit*>(Inst.TheDef->getValueInit("Pattern"))) {
- ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern");
- if (LI && LI->getSize() > 0) {
- DagInit *Dag = (DagInit *)LI->getElement(0);
- DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator());
- if (OpDef) {
- Record *Operator = OpDef->getDef();
- if (Operator->isSubClassOf("SDNode")) {
- const std::string Opcode = Operator->getValueAsString("Opcode");
- if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE")
- isStore = true;
- }
- }
- }
- }
+ << Inst.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef)
+ << ",\t\"" << Inst.TheDef->getName() << "\", 0";
// Emit all of the target indepedent flags...
- if (Inst.isReturn) OS << "|M_RET_FLAG";
- if (Inst.isBranch) OS << "|M_BRANCH_FLAG";
- if (Inst.isIndirectBranch) OS << "|M_INDIRECT_FLAG";
- if (Inst.isBarrier) OS << "|M_BARRIER_FLAG";
- if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
- if (Inst.isCall) OS << "|M_CALL_FLAG";
- if (Inst.isLoad) OS << "|M_LOAD_FLAG";
- if (Inst.isStore || isStore) OS << "|M_STORE_FLAG";
- if (Inst.isPredicable) OS << "|M_PREDICABLE";
- if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
- if (Inst.isCommutable) OS << "|M_COMMUTABLE";
- if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
- if (Inst.isReMaterializable) OS << "|M_REMATERIALIZIBLE";
- if (Inst.isNotDuplicable) OS << "|M_NOT_DUPLICABLE";
- if (Inst.hasOptionalDef) OS << "|M_HAS_OPTIONAL_DEF";
- if (Inst.usesCustomDAGSchedInserter)
- OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
- if (Inst.hasVariableNumberOfOperands)
- OS << "|M_VARIABLE_OPS";
- OS << ", 0";
+ if (Inst.isReturn) OS << "|(1<<TID::Return)";
+ if (Inst.isBranch) OS << "|(1<<TID::Branch)";
+ if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)";
+ if (Inst.isBarrier) OS << "|(1<<TID::Barrier)";
+ if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
+ if (Inst.isCall) OS << "|(1<<TID::Call)";
+ if (Inst.canFoldAsLoad) OS << "|(1<<TID::FoldableAsLoad)";
+ if (Inst.mayLoad) OS << "|(1<<TID::MayLoad)";
+ if (Inst.mayStore) OS << "|(1<<TID::MayStore)";
+ if (Inst.isPredicable) OS << "|(1<<TID::Predicable)";
+ if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)";
+ if (Inst.isCommutable) OS << "|(1<<TID::Commutable)";
+ if (Inst.isTerminator) OS << "|(1<<TID::Terminator)";
+ if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)";
+ if (Inst.isNotDuplicable) OS << "|(1<<TID::NotDuplicable)";
+ if (Inst.hasOptionalDef) OS << "|(1<<TID::HasOptionalDef)";
+ if (Inst.usesCustomInserter) OS << "|(1<<TID::UsesCustomInserter)";
+ if (Inst.isVariadic) OS << "|(1<<TID::Variadic)";
+ if (Inst.hasSideEffects) OS << "|(1<<TID::UnmodeledSideEffects)";
+ if (Inst.isAsCheapAsAMove) OS << "|(1<<TID::CheapAsAMove)";
+ if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<TID::ExtraSrcRegAllocReq)";
+ if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<TID::ExtraDefRegAllocReq)";
// Emit all of the target-specific flags...
- ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields");
- ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
- if (LI->getSize() != Shift->getSize())
- throw "Lengths of " + InstrInfo->getName() +
- ":(TargetInfoFields, TargetInfoPositions) must be equal!";
-
- for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
- emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
- dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
-
+ BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
+ if (!TSF) throw "no TSFlags?";
+ uint64_t Value = 0;
+ for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
+ if (BitInit *Bit = dynamic_cast<BitInit*>(TSF->getBit(i)))
+ Value |= uint64_t(Bit->getValue()) << i;
+ else
+ throw "Invalid TSFlags bit in " + Inst.TheDef->getName();
+ }
+ OS << ", 0x";
+ OS.write_hex(Value);
OS << ", ";
// Emit the implicit uses and defs lists...
else
OS << "ImplicitList" << EmittedLists[DefList] << ", ";
+ std::map<Record*, unsigned>::iterator BI = BarriersMap.find(Inst.TheDef);
+ if (BI == BarriersMap.end())
+ OS << "NULL, ";
+ else
+ OS << "Barriers" << BI->second << ", ";
+
// Emit the operand info.
std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
if (OperandInfo.empty())
OS << "0";
else
- OS << "OperandInfo" << OpInfo[OperandInfo];
-
- OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
-}
-
-struct LessRecord {
- bool operator()(const Record *Rec1, const Record *Rec2) const {
- return Rec1->getName() < Rec2->getName();
- }
-};
-void InstrInfoEmitter::GatherItinClasses() {
- std::vector<Record*> DefList =
- Records.getAllDerivedDefinitions("InstrItinClass");
- IsItineraries = !DefList.empty();
-
- if (!IsItineraries) return;
-
- std::sort(DefList.begin(), DefList.end(), LessRecord());
-
- for (unsigned i = 0, N = DefList.size(); i < N; i++) {
- Record *Def = DefList[i];
- ItinClassMap[Def->getName()] = i;
- }
-}
-
-unsigned InstrInfoEmitter::ItinClassNumber(std::string ItinName) {
- return ItinClassMap[ItinName];
-}
-
-void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
- IntInit *ShiftInt, std::ostream &OS) {
- if (Val == 0 || ShiftInt == 0)
- throw std::string("Illegal value or shift amount in TargetInfo*!");
- RecordVal *RV = R->getValue(Val->getValue());
- int Shift = ShiftInt->getValue();
-
- if (RV == 0 || RV->getValue() == 0) {
- // This isn't an error if this is a builtin instruction.
- if (R->getName() != "PHI" &&
- R->getName() != "INLINEASM" &&
- R->getName() != "LABEL" &&
- R->getName() != "EXTRACT_SUBREG" &&
- R->getName() != "INSERT_SUBREG")
- throw R->getName() + " doesn't have a field named '" +
- Val->getValue() + "'!";
- return;
- }
-
- Init *Value = RV->getValue();
- if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
- if (BI->getValue()) OS << "|(1<<" << Shift << ")";
- return;
- } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
- // Convert the Bits to an integer to print...
- Init *I = BI->convertInitializerTo(new IntRecTy());
- if (I)
- if (IntInit *II = dynamic_cast<IntInit*>(I)) {
- if (II->getValue()) {
- if (Shift)
- OS << "|(" << II->getValue() << "<<" << Shift << ")";
- else
- OS << "|" << II->getValue();
- }
- return;
- }
+ OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
- } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
- if (II->getValue()) {
- if (Shift)
- OS << "|(" << II->getValue() << "<<" << Shift << ")";
- else
- OS << II->getValue();
- }
- return;
- }
-
- cerr << "Unhandled initializer: " << *Val << "\n";
- throw "In record '" + R->getName() + "' for TSFlag emission.";
+ OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
}
-
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