#include "InstrInfoEmitter.h"
#include "CodeGenTarget.h"
#include "Record.h"
+#include "llvm/ADT/StringExtras.h"
#include <algorithm>
-#include <iostream>
using namespace llvm;
static void PrintDefList(const std::vector<Record*> &Uses,
- unsigned Num, std::ostream &OS) {
+ unsigned Num, raw_ostream &OS) {
OS << "static const unsigned ImplicitList" << Num << "[] = { ";
for (unsigned i = 0, e = Uses.size(); i != e; ++i)
OS << getQualifiedName(Uses[i]) << ", ";
OS << "0 };\n";
}
+static void PrintBarriers(std::vector<Record*> &Barriers,
+ unsigned Num, raw_ostream &OS) {
+ OS << "static const TargetRegisterClass* Barriers" << Num << "[] = { ";
+ for (unsigned i = 0, e = Barriers.size(); i != e; ++i)
+ OS << "&" << getQualifiedName(Barriers[i]) << "RegClass, ";
+ OS << "NULL };\n";
+}
+
//===----------------------------------------------------------------------===//
// Instruction Itinerary Information.
//===----------------------------------------------------------------------===//
-struct RecordNameComparator {
- bool operator()(const Record *Rec1, const Record *Rec2) const {
- return Rec1->getName() < Rec2->getName();
- }
-};
-
void InstrInfoEmitter::GatherItinClasses() {
std::vector<Record*> DefList =
Records.getAllDerivedDefinitions("InstrItinClass");
- std::sort(DefList.begin(), DefList.end(), RecordNameComparator());
+ std::sort(DefList.begin(), DefList.end(), LessRecord());
for (unsigned i = 0, N = DefList.size(); i < N; i++)
ItinClassMap[DefList[i]->getName()] = i;
if (OpR->isSubClassOf("RegisterClass"))
Res += getQualifiedName(OpR) + "RegClassID, ";
+ else if (OpR->isSubClassOf("PointerLikeRegClass"))
+ Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
else
Res += "0, ";
+
// Fill in applicable flags.
Res += "0";
// Ptr value whose register class is resolved via callback.
- if (OpR->getName() == "ptr_rc")
+ if (OpR->isSubClassOf("PointerLikeRegClass"))
Res += "|(1<<TOI::LookupPtrRegClass)";
// Predicate operands. Check to see if the original unexpanded operand
Res += "|(1<<TOI::OptionalDef)";
// Fill in constraint info.
- Res += ", " + Inst.OperandList[i].Constraints[j];
+ Res += ", ";
+
+ const CodeGenInstruction::ConstraintInfo &Constraint =
+ Inst.OperandList[i].Constraints[j];
+ if (Constraint.isNone())
+ Res += "0";
+ else if (Constraint.isEarlyClobber())
+ Res += "(1 << TOI::EARLY_CLOBBER)";
+ else {
+ assert(Constraint.isTied());
+ Res += "((" + utostr(Constraint.getTiedOperand()) +
+ " << 16) | (1 << TOI::TIED_TO))";
+ }
+
Result.push_back(Res);
}
}
return Result;
}
-void InstrInfoEmitter::EmitOperandInfo(std::ostream &OS,
+void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
OperandInfoMapTy &OperandInfoIDs) {
// ID #0 is for no operand info.
unsigned OperandListNum = 0;
const CodeGenTarget &Target = CDP.getTargetInfo();
for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
E = Target.inst_end(); II != E; ++II) {
- std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
+ std::vector<std::string> OperandInfo = GetOperandInfo(**II);
unsigned &N = OperandInfoIDs[OperandInfo];
if (N != 0) continue;
}
}
-//===----------------------------------------------------------------------===//
-// Instruction Analysis
-//===----------------------------------------------------------------------===//
-
-class InstAnalyzer {
- const CodeGenDAGPatterns &CDP;
- bool &mayStore;
- bool &mayLoad;
- bool &NeverHasSideEffects;
-public:
- InstAnalyzer(const CodeGenDAGPatterns &cdp,
- bool &maystore, bool &mayload, bool &nhse)
- : CDP(cdp), mayStore(maystore), mayLoad(mayload), NeverHasSideEffects(nhse){
- }
-
- void Analyze(Record *InstRecord) {
- const TreePattern *Pattern = CDP.getInstruction(InstRecord).getPattern();
- if (Pattern == 0) return; // No pattern.
-
- // Assume there is no side-effect unless we see one.
- NeverHasSideEffects = true;
-
- // FIXME: Assume only the first tree is the pattern. The others are clobber
- // nodes.
- AnalyzeNode(Pattern->getTree(0));
- }
-
-private:
- void AnalyzeNode(const TreePatternNode *N) {
- if (N->isLeaf())
- return;
-
- if (N->getOperator()->getName() != "set") {
- // Get information about the SDNode for the operator.
- const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N->getOperator());
-
- // If node writes to memory, it obviously stores to memory.
- if (OpInfo.hasProperty(SDNPMayStore)) {
- mayStore = true;
- } else if (const CodeGenIntrinsic *IntInfo = N->getIntrinsicInfo(CDP)) {
- // If this is an intrinsic, analyze it.
- if (IntInfo->ModRef >= CodeGenIntrinsic::WriteArgMem)
- mayStore = true;// Intrinsics that can write to memory are 'mayStore'.
+void InstrInfoEmitter::DetectRegisterClassBarriers(std::vector<Record*> &Defs,
+ const std::vector<CodeGenRegisterClass> &RCs,
+ std::vector<Record*> &Barriers) {
+ std::set<Record*> DefSet;
+ unsigned NumDefs = Defs.size();
+ for (unsigned i = 0; i < NumDefs; ++i)
+ DefSet.insert(Defs[i]);
+
+ for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
+ const CodeGenRegisterClass &RC = RCs[i];
+ unsigned NumRegs = RC.Elements.size();
+ if (NumRegs > NumDefs)
+ continue; // Can't possibly clobber this RC.
+
+ bool Clobber = true;
+ for (unsigned j = 0; j < NumRegs; ++j) {
+ Record *Reg = RC.Elements[j];
+ if (!DefSet.count(Reg)) {
+ Clobber = false;
+ break;
}
}
-
- for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i)
- AnalyzeNode(N->getChild(i));
+ if (Clobber)
+ Barriers.push_back(RC.TheDef);
}
-
-};
-
-void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst,
- bool &mayStore, bool &mayLoad,
- bool &NeverHasSideEffects) {
- mayStore = mayLoad = NeverHasSideEffects = false;
-
- InstAnalyzer(CDP, mayStore, mayLoad,NeverHasSideEffects).Analyze(Inst.TheDef);
-
- // InstAnalyzer only correctly analyzes mayStore so far.
- if (Inst.mayStore) { // If the .td file explicitly sets mayStore, use it.
- // If we decided that this is a store from the pattern, then the .td file
- // entry is redundant.
- if (mayStore)
- fprintf(stderr,
- "Warning: mayStore flag explicitly set on instruction '%s'"
- " but flag already inferred from pattern.\n",
- Inst.TheDef->getName().c_str());
- mayStore = true;
- }
-
- // These two override everything.
- mayLoad = Inst.mayLoad;
- NeverHasSideEffects = Inst.neverHasSideEffects;
-
-#if 0
- // If the .td file explicitly says there is no side effect, believe it.
- if (Inst.neverHasSideEffects)
- NeverHasSideEffects = true;
-#endif
}
-
//===----------------------------------------------------------------------===//
// Main Output.
//===----------------------------------------------------------------------===//
// run - Emit the main instruction description records for the target...
-void InstrInfoEmitter::run(std::ostream &OS) {
+void InstrInfoEmitter::run(raw_ostream &OS) {
GatherItinClasses();
EmitSourceFileHeader("Target Instruction Descriptors", OS);
OS << "namespace llvm {\n\n";
- CodeGenTarget Target;
+ CodeGenTarget &Target = CDP.getTargetInfo();
const std::string &TargetName = Target.getName();
Record *InstrInfo = Target.getInstructionSet();
+ const std::vector<CodeGenRegisterClass> &RCs = Target.getRegisterClasses();
// Keep track of all of the def lists we have emitted already.
std::map<std::vector<Record*>, unsigned> EmittedLists;
unsigned ListNumber = 0;
+ std::map<std::vector<Record*>, unsigned> EmittedBarriers;
+ unsigned BarrierNumber = 0;
+ std::map<Record*, unsigned> BarriersMap;
// Emit all of the instruction's implicit uses and defs.
for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
E = Target.inst_end(); II != E; ++II) {
- Record *Inst = II->second.TheDef;
+ Record *Inst = (*II)->TheDef;
std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
if (!Uses.empty()) {
unsigned &IL = EmittedLists[Uses];
}
std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
if (!Defs.empty()) {
+ std::vector<Record*> RCBarriers;
+ DetectRegisterClassBarriers(Defs, RCs, RCBarriers);
+ if (!RCBarriers.empty()) {
+ unsigned &IB = EmittedBarriers[RCBarriers];
+ if (!IB) PrintBarriers(RCBarriers, IB = ++BarrierNumber, OS);
+ BarriersMap.insert(std::make_pair(Inst, IB));
+ }
+
unsigned &IL = EmittedLists[Defs];
if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
}
//
OS << "\nstatic const TargetInstrDesc " << TargetName
<< "Insts[] = {\n";
- std::vector<const CodeGenInstruction*> NumberedInstructions;
- Target.getInstructionsByEnumValue(NumberedInstructions);
+ const std::vector<const CodeGenInstruction*> &NumberedInstructions =
+ Target.getInstructionsByEnumValue();
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
- OperandInfoIDs, OS);
+ BarriersMap, OperandInfoIDs, OS);
OS << "};\n";
OS << "} // End llvm namespace \n";
}
void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
Record *InstrInfo,
std::map<std::vector<Record*>, unsigned> &EmittedLists,
+ std::map<Record*, unsigned> &BarriersMap,
const OperandInfoMapTy &OpInfo,
- std::ostream &OS) {
- // Determine properties of the instruction from its pattern.
- bool mayStore, mayLoad, NeverHasSideEffects;
- InferFromPattern(Inst, mayStore, mayLoad, NeverHasSideEffects);
-
- if (NeverHasSideEffects && Inst.mayHaveSideEffects) {
- std::cerr << "error: Instruction '" << Inst.TheDef->getName()
- << "' is marked with 'mayHaveSideEffects', but it can never have them!\n";
- exit(1);
- }
-
+ raw_ostream &OS) {
int MinOperands = 0;
if (!Inst.OperandList.empty())
// Each logical operand can be multiple MI operands.
MinOperands = Inst.OperandList.back().MIOperandNo +
Inst.OperandList.back().MINumOperands;
-
+
OS << " { ";
OS << Num << ",\t" << MinOperands << ",\t"
<< Inst.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef)
<< ",\t\"" << Inst.TheDef->getName() << "\", 0";
// Emit all of the target indepedent flags...
- if (Inst.isReturn) OS << "|(1<<TID::Return)";
- if (Inst.isBranch) OS << "|(1<<TID::Branch)";
- if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)";
- if (Inst.isBarrier) OS << "|(1<<TID::Barrier)";
- if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
- if (Inst.isCall) OS << "|(1<<TID::Call)";
- if (Inst.isSimpleLoad) OS << "|(1<<TID::SimpleLoad)";
- if (mayLoad) OS << "|(1<<TID::MayLoad)";
- if (mayStore) OS << "|(1<<TID::MayStore)";
- if (Inst.isImplicitDef)OS << "|(1<<TID::ImplicitDef)";
- if (Inst.isPredicable) OS << "|(1<<TID::Predicable)";
+ if (Inst.isReturn) OS << "|(1<<TID::Return)";
+ if (Inst.isBranch) OS << "|(1<<TID::Branch)";
+ if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)";
+ if (Inst.isBarrier) OS << "|(1<<TID::Barrier)";
+ if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
+ if (Inst.isCall) OS << "|(1<<TID::Call)";
+ if (Inst.canFoldAsLoad) OS << "|(1<<TID::FoldableAsLoad)";
+ if (Inst.mayLoad) OS << "|(1<<TID::MayLoad)";
+ if (Inst.mayStore) OS << "|(1<<TID::MayStore)";
+ if (Inst.isPredicable) OS << "|(1<<TID::Predicable)";
if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)";
- if (Inst.isCommutable) OS << "|(1<<TID::Commutable)";
- if (Inst.isTerminator) OS << "|(1<<TID::Terminator)";
+ if (Inst.isCommutable) OS << "|(1<<TID::Commutable)";
+ if (Inst.isTerminator) OS << "|(1<<TID::Terminator)";
if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)";
if (Inst.isNotDuplicable) OS << "|(1<<TID::NotDuplicable)";
if (Inst.hasOptionalDef) OS << "|(1<<TID::HasOptionalDef)";
- if (Inst.usesCustomDAGSchedInserter)
- OS << "|(1<<TID::UsesCustomDAGSchedInserter)";
+ if (Inst.usesCustomInserter) OS << "|(1<<TID::UsesCustomInserter)";
if (Inst.isVariadic) OS << "|(1<<TID::Variadic)";
- if (Inst.mayHaveSideEffects) OS << "|(1<<TID::MayHaveSideEffects)";
- if (NeverHasSideEffects) OS << "|(1<<TID::NeverHasSideEffects)";
- OS << ", 0";
+ if (Inst.hasSideEffects) OS << "|(1<<TID::UnmodeledSideEffects)";
+ if (Inst.isAsCheapAsAMove) OS << "|(1<<TID::CheapAsAMove)";
+ if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<TID::ExtraSrcRegAllocReq)";
+ if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<TID::ExtraDefRegAllocReq)";
// Emit all of the target-specific flags...
- ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields");
- ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
- if (LI->getSize() != Shift->getSize())
- throw "Lengths of " + InstrInfo->getName() +
- ":(TargetInfoFields, TargetInfoPositions) must be equal!";
-
- for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
- emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
- dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
-
+ BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
+ if (!TSF) throw "no TSFlags?";
+ uint64_t Value = 0;
+ for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
+ if (BitInit *Bit = dynamic_cast<BitInit*>(TSF->getBit(i)))
+ Value |= uint64_t(Bit->getValue()) << i;
+ else
+ throw "Invalid TSFlags bit in " + Inst.TheDef->getName();
+ }
+ OS << ", 0x";
+ OS.write_hex(Value);
OS << ", ";
// Emit the implicit uses and defs lists...
else
OS << "ImplicitList" << EmittedLists[DefList] << ", ";
+ std::map<Record*, unsigned>::iterator BI = BarriersMap.find(Inst.TheDef);
+ if (BI == BarriersMap.end())
+ OS << "NULL, ";
+ else
+ OS << "Barriers" << BI->second << ", ";
+
// Emit the operand info.
std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
if (OperandInfo.empty())
OS << "0";
else
OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
-
- OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
-}
-
-
-void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
- IntInit *ShiftInt, std::ostream &OS) {
- if (Val == 0 || ShiftInt == 0)
- throw std::string("Illegal value or shift amount in TargetInfo*!");
- RecordVal *RV = R->getValue(Val->getValue());
- int Shift = ShiftInt->getValue();
-
- if (RV == 0 || RV->getValue() == 0) {
- // This isn't an error if this is a builtin instruction.
- if (R->getName() != "PHI" &&
- R->getName() != "INLINEASM" &&
- R->getName() != "LABEL" &&
- R->getName() != "EXTRACT_SUBREG" &&
- R->getName() != "INSERT_SUBREG")
- throw R->getName() + " doesn't have a field named '" +
- Val->getValue() + "'!";
- return;
- }
-
- Init *Value = RV->getValue();
- if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
- if (BI->getValue()) OS << "|(1<<" << Shift << ")";
- return;
- } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
- // Convert the Bits to an integer to print...
- Init *I = BI->convertInitializerTo(new IntRecTy());
- if (I)
- if (IntInit *II = dynamic_cast<IntInit*>(I)) {
- if (II->getValue()) {
- if (Shift)
- OS << "|(" << II->getValue() << "<<" << Shift << ")";
- else
- OS << "|" << II->getValue();
- }
- return;
- }
- } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
- if (II->getValue()) {
- if (Shift)
- OS << "|(" << II->getValue() << "<<" << Shift << ")";
- else
- OS << II->getValue();
- }
- return;
- }
-
- std::cerr << "Unhandled initializer: " << *Val << "\n";
- throw "In record '" + R->getName() + "' for TSFlag emission.";
+ OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
}
-
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