//
//===----------------------------------------------------------------------===//
//
-// This tablegen backend emits a "fast" instruction selector.
+// This tablegen backend emits code for use by the "fast" instruction
+// selection algorithm. See the comments at the top of
+// lib/CodeGen/SelectionDAG/FastISel.cpp for background.
//
-// This instruction selection method is designed to emit very poor code
-// quickly. Also, it is not designed to do much lowering, so most illegal
-// types (e.g. i64 on 32-bit targets) and operations (e.g. calls) are not
-// supported and cannot easily be added. Blocks containing operations
-// that are not supported need to be handled by a more capable selector,
-// such as the SelectionDAG selector.
+// This file scans through the target's tablegen instruction-info files
+// and extracts instructions with obvious-looking patterns, and it emits
+// code to look up these instructions by type and operator.
//
-// The intended use for "fast" instruction selection is "-O0" mode
-// compilation, where the quality of the generated code is irrelevant when
-// weighed against the speed at which the code can be generated.
-//
-// If compile time is so important, you might wonder why we don't just
-// skip codegen all-together, emit LLVM bytecode files, and execute them
-// with an interpreter. The answer is that it would complicate linking and
-// debugging, and also because that isn't how a compiler is expected to
-// work in some circles.
-//
-// If you need better generated code or more lowering than what this
-// instruction selector provides, use the SelectionDAG (DAGISel) instruction
-// selector instead. If you're looking here because SelectionDAG isn't fast
-// enough, consider looking into improving the SelectionDAG infastructure
-// instead. At the time of this writing there remain several major
-// opportunities for improvement.
-//
//===----------------------------------------------------------------------===//
#include "FastISelEmitter.h"
#include "Record.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Support/Streams.h"
#include "llvm/ADT/VectorExtras.h"
using namespace llvm;
for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
TreePatternNode *Op = InstPatNode->getChild(i);
// For now, filter out any operand with a predicate.
- if (!Op->getPredicateFn().empty())
+ if (!Op->getPredicateFns().empty())
return false;
// For now, filter out any operand with multiple values.
if (Op->getExtTypes().size() != 1)
if (!Op->isLeaf()) {
if (Op->getOperator()->getName() == "imm") {
Operands.push_back("i");
- return true;
+ continue;
}
if (Op->getOperator()->getName() == "fpimm") {
Operands.push_back("f");
- return true;
+ continue;
}
// For now, ignore other non-leaf nodes.
return false;
return false;
Record *OpLeafRec = OpDI->getDef();
// For now, the only other thing we accept is register operands.
-
+
const CodeGenRegisterClass *RC = 0;
if (OpLeafRec->isSubClassOf("RegisterClass"))
RC = &Target.getRegisterClass(OpLeafRec);
return true;
}
- void PrintParameters(std::ostream &OS) const {
+ void PrintParameters(raw_ostream &OS) const {
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
if (Operands[i] == "r") {
OS << "unsigned Op" << i;
}
}
- void PrintArguments(std::ostream &OS,
+ void PrintArguments(raw_ostream &OS,
const std::vector<std::string>& PR) const {
assert(PR.size() == Operands.size());
+ bool PrintedArg = false;
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
- if (PR[i] != "") {
- OS << PR[i];
- } else if (Operands[i] == "r") {
+ if (PR[i] != "")
+ // Implicit physical register operand.
+ continue;
+
+ if (PrintedArg)
+ OS << ", ";
+ if (Operands[i] == "r") {
OS << "Op" << i;
+ PrintedArg = true;
} else if (Operands[i] == "i") {
OS << "imm" << i;
+ PrintedArg = true;
} else if (Operands[i] == "f") {
OS << "f" << i;
+ PrintedArg = true;
} else {
assert("Unknown operand kind!");
abort();
}
- if (i + 1 != e)
- OS << ", ";
}
}
- void PrintArguments(std::ostream &OS) const {
+ void PrintArguments(raw_ostream &OS) const {
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
if (Operands[i] == "r") {
OS << "Op" << i;
}
- void PrintManglingSuffix(std::ostream &OS) const {
+ void PrintManglingSuffix(raw_ostream &OS,
+ const std::vector<std::string>& PR) const {
+ for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
+ if (PR[i] != "")
+ // Implicit physical register operand. e.g. Instruction::Mul expect to
+ // select to a binary op. On x86, mul may take a single operand with
+ // the other operand being implicit. We must emit something that looks
+ // like a binary instruction except for the very inner FastEmitInst_*
+ // call.
+ continue;
+ OS << Operands[i];
+ }
+ }
+
+ void PrintManglingSuffix(raw_ostream &OS) const {
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
OS << Operands[i];
}
explicit FastISelMap(std::string InstNS);
void CollectPatterns(CodeGenDAGPatterns &CGP);
- void PrintClass(std::ostream &OS);
- void PrintFunctionDefinitions(std::ostream &OS);
+ void PrintFunctionDefinitions(raw_ostream &OS);
};
}
continue;
// For now, filter out any instructions with predicates.
- if (!InstPatNode->getPredicateFn().empty())
+ if (!InstPatNode->getPredicateFns().empty())
continue;
// Check all the operands.
}
}
-void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) {
+void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) {
// Now emit code for all the patterns that we collected.
for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
OE = SimplePatterns.end(); OI != OE; ++OI) {
OS << " return FastEmitInst_";
if (Memo.SubRegNo == (unsigned char)~0) {
- Operands.PrintManglingSuffix(OS);
+ Operands.PrintManglingSuffix(OS, *Memo.PhysRegs);
OS << "(" << InstNS << Memo.Name << ", ";
OS << InstNS << Memo.RC->getName() << "RegisterClass";
if (!Operands.empty())
Operands.PrintArguments(OS, *Memo.PhysRegs);
OS << ");\n";
} else {
- OS << "extractsubreg(Op0, ";
+ OS << "extractsubreg(" << getName(RetVT);
+ OS << ", Op0, ";
OS << (unsigned)Memo.SubRegNo;
OS << ");\n";
}
if (HasPred)
- OS << "}\n";
+ OS << " }\n";
}
// Return 0 if none of the predicates were satisfied.
<< getLegalCName(Opcode) << "_"
<< getLegalCName(getName(VT)) << "_";
Operands.PrintManglingSuffix(OS);
- OS << "(MVT::SimpleValueType RetVT";
+ OS << "(MVT RetVT";
if (!Operands.empty())
OS << ", ";
Operands.PrintParameters(OS);
- OS << ") {\nswitch (RetVT) {\n";
+ OS << ") {\nswitch (RetVT.SimpleTy) {\n";
for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
RI != RE; ++RI) {
MVT::SimpleValueType RetVT = RI->first;
<< getLegalCName(Opcode) << "_"
<< getLegalCName(getName(VT)) << "_";
Operands.PrintManglingSuffix(OS);
- OS << "(MVT::SimpleValueType RetVT";
+ OS << "(MVT RetVT";
if (!Operands.empty())
OS << ", ";
Operands.PrintParameters(OS);
OS << ") {\n";
- OS << " if (RetVT != " << getName(RM.begin()->first)
+ OS << " if (RetVT.SimpleTy != " << getName(RM.begin()->first)
<< ")\n return 0;\n";
const PredMap &PM = RM.begin()->second;
// Emit code for each possible instruction. There may be
// multiple if there are subtarget concerns.
- for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE; ++PI) {
+ for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE;
+ ++PI) {
std::string PredicateCheck = PI->first;
const InstructionMemo &Memo = PI->second;
OS << " return FastEmitInst_";
if (Memo.SubRegNo == (unsigned char)~0) {
- Operands.PrintManglingSuffix(OS);
+ Operands.PrintManglingSuffix(OS, *Memo.PhysRegs);
OS << "(" << InstNS << Memo.Name << ", ";
OS << InstNS << Memo.RC->getName() << "RegisterClass";
if (!Operands.empty())
Operands.PrintArguments(OS, *Memo.PhysRegs);
OS << ");\n";
} else {
- OS << "extractsubreg(Op0, ";
+ OS << "extractsubreg(RetVT, Op0, ";
OS << (unsigned)Memo.SubRegNo;
OS << ");\n";
}
OS << "unsigned FastEmit_"
<< getLegalCName(Opcode) << "_";
Operands.PrintManglingSuffix(OS);
- OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT";
+ OS << "(MVT VT, MVT RetVT";
if (!Operands.empty())
OS << ", ";
Operands.PrintParameters(OS);
OS << ") {\n";
- OS << " switch (VT) {\n";
+ OS << " switch (VT.SimpleTy) {\n";
for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
TI != TE; ++TI) {
MVT::SimpleValueType VT = TI->first;
// on opcode and type.
OS << "unsigned FastEmit_";
Operands.PrintManglingSuffix(OS);
- OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT, ISD::NodeType Opcode";
+ OS << "(MVT VT, MVT RetVT, ISD::NodeType Opcode";
if (!Operands.empty())
OS << ", ";
Operands.PrintParameters(OS);
}
}
-void FastISelEmitter::run(std::ostream &OS) {
+void FastISelEmitter::run(raw_ostream &OS) {
const CodeGenTarget &Target = CGP.getTargetInfo();
// Determine the target's namespace name.
projects / oota-llvm.git / blobdiff