DenseMap<TreePattern *, unsigned> ImmIDs;
std::vector<TreePredicateFn> PredsByName;
public:
-
+
unsigned getIDFor(TreePredicateFn Pred) {
unsigned &Entry = ImmIDs[Pred.getOrigPatFragRecord()];
if (Entry == 0) {
}
return Entry-1;
}
-
+
const TreePredicateFn &getPredicate(unsigned i) {
assert(i < PredsByName.size());
return PredsByName[i];
}
-
+
typedef std::vector<TreePredicateFn>::const_iterator iterator;
iterator begin() const { return PredsByName.begin(); }
iterator end() const { return PredsByName.end(); }
-
+
};
} // End anonymous namespace
enum { OK_Reg, OK_FP, OK_Imm, OK_Invalid = -1 };
char Repr;
public:
-
+
OpKind() : Repr(OK_Invalid) {}
-
+
bool operator<(OpKind RHS) const { return Repr < RHS.Repr; }
bool operator==(OpKind RHS) const { return Repr == RHS.Repr; }
"Too many integer predicates for the 'Repr' char");
OpKind K; K.Repr = OK_Imm+V; return K;
}
-
+
bool isReg() const { return Repr == OK_Reg; }
bool isFP() const { return Repr == OK_FP; }
bool isImm() const { return Repr >= OK_Imm; }
-
+
unsigned getImmCode() const { assert(isImm()); return Repr-OK_Imm; }
-
+
void printManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates,
bool StripImmCodes) const {
if (isReg())
}
}
};
-
-
+
+
SmallVector<OpKind, 3> Operands;
bool operator<(const OperandsSignature &O) const {
return true;
return false;
}
-
+
/// getWithoutImmCodes - Return a copy of this with any immediate codes forced
/// to zero.
OperandsSignature getWithoutImmCodes() const {
Result.Operands.push_back(OpKind::getImm(0));
return Result;
}
-
+
void emitImmediatePredicate(raw_ostream &OS, ImmPredicateSet &ImmPredicates) {
bool EmittedAnything = false;
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
if (!Operands[i].isImm()) continue;
-
+
unsigned Code = Operands[i].getImmCode();
if (Code == 0) continue;
-
+
if (EmittedAnything)
OS << " &&\n ";
-
+
TreePredicateFn PredFn = ImmPredicates.getPredicate(Code-1);
-
+
// Emit the type check.
OS << "VT == "
<< getEnumName(PredFn.getOrigPatFragRecord()->getTree(0)->getType(0))
<< " && ";
-
-
+
+
OS << PredFn.getFnName() << "(imm" << i <<')';
EmittedAnything = true;
}
}
-
+
/// initialize - Examine the given pattern and initialize the contents
/// of the Operands array accordingly. Return true if all the operands
/// are supported, false otherwise.
///
bool initialize(TreePatternNode *InstPatNode, const CodeGenTarget &Target,
MVT::SimpleValueType VT,
- ImmPredicateSet &ImmediatePredicates) {
+ ImmPredicateSet &ImmediatePredicates,
+ const CodeGenRegisterClass *OrigDstRC) {
if (InstPatNode->isLeaf())
return false;
-
+
if (InstPatNode->getOperator()->getName() == "imm") {
Operands.push_back(OpKind::getImm(0));
return true;
}
-
+
if (InstPatNode->getOperator()->getName() == "fpimm") {
Operands.push_back(OpKind::getFP());
return true;
}
- const CodeGenRegisterClass *DstRC = 0;
+ const CodeGenRegisterClass *DstRC = nullptr;
for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
TreePatternNode *Op = InstPatNode->getChild(i);
Record *Rec = PredFn.getOrigPatFragRecord()->getRecord();
if (Rec->getValueAsBit("FastIselShouldIgnore"))
return false;
-
+
PredNo = ImmediatePredicates.getIDFor(PredFn)+1;
}
-
+
// Handle unmatched immediate sizes here.
//if (Op->getType(0) != VT)
// return false;
-
+
Operands.push_back(OpKind::getImm(PredNo));
continue;
}
-
+
// For now, filter out any operand with a predicate.
// For now, filter out any operand with multiple values.
if (!Op->getPredicateFns().empty() || Op->getNumTypes() != 1)
// For now, ignore other non-leaf nodes.
return false;
}
-
+
assert(Op->hasTypeSet(0) && "Type infererence not done?");
// For now, all the operands must have the same type (if they aren't
if (!OpDI)
return false;
Record *OpLeafRec = OpDI->getDef();
-
+
// For now, the only other thing we accept is register operands.
- const CodeGenRegisterClass *RC = 0;
+ const CodeGenRegisterClass *RC = nullptr;
if (OpLeafRec->isSubClassOf("RegisterOperand"))
OpLeafRec = OpLeafRec->getValueAsDef("RegClass");
if (OpLeafRec->isSubClassOf("RegisterClass"))
RC = &Target.getRegisterClass(OpLeafRec);
else if (OpLeafRec->isSubClassOf("Register"))
RC = Target.getRegBank().getRegClassForRegister(OpLeafRec);
- else
+ else if (OpLeafRec->isSubClassOf("ValueType")) {
+ RC = OrigDstRC;
+ } else
return false;
// For now, this needs to be a register class of some sort.
std::map<OperandsSignature, std::vector<OperandsSignature> >
SignaturesWithConstantForms;
-
+
std::string InstNS;
ImmPredicateSet ImmediatePredicates;
public:
// For now, ignore instructions where the first operand is not an
// output register.
- const CodeGenRegisterClass *DstRC = 0;
+ const CodeGenRegisterClass *DstRC = nullptr;
std::string SubRegNo;
if (Op->getName() != "EXTRACT_SUBREG") {
Record *Op0Rec = II.Operands[0].Rec;
// Check all the operands.
OperandsSignature Operands;
- if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates))
+ if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates,
+ DstRC))
continue;
std::vector<std::string>* PhysRegInputs = new std::vector<std::string>();
SubRegNo,
PhysRegInputs
};
-
+
if (SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck))
PrintFatalError(Pattern.getSrcRecord()->getLoc(),
"Duplicate record in FastISel table!");
SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo;
-
+
// If any of the operands were immediates with predicates on them, strip
// them down to a signature that doesn't have predicates so that we can
// associate them with the stripped predicate version.
void FastISelMap::printImmediatePredicates(raw_ostream &OS) {
if (ImmediatePredicates.begin() == ImmediatePredicates.end())
return;
-
+
OS << "\n// FastEmit Immediate Predicate functions.\n";
for (ImmPredicateSet::iterator I = ImmediatePredicates.begin(),
E = ImmediatePredicates.end(); I != E; ++I) {
OS << "static bool " << I->getFnName() << "(int64_t Imm) {\n";
OS << I->getImmediatePredicateCode() << "\n}\n";
}
-
+
OS << "\n\n";
}
for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
if ((*Memo.PhysRegs)[i] != "")
- OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, "
+ OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, "
<< "TII.get(TargetOpcode::COPY), "
<< (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
}
for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
if ((*Memo.PhysRegs)[i] != "")
- OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, "
+ OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, "
<< "TII.get(TargetOpcode::COPY), "
<< (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
}
OS << ", ";
Operands.PrintParameters(OS);
OS << ") {\n";
-
- // If there are any forms of this signature available that operand on
- // constrained forms of the immediate (e.g. 32-bit sext immediate in a
+
+ // If there are any forms of this signature available that operate on
+ // constrained forms of the immediate (e.g., 32-bit sext immediate in a
// 64-bit operand), check them first.
-
+
std::map<OperandsSignature, std::vector<OperandsSignature> >::iterator MI
= SignaturesWithConstantForms.find(Operands);
if (MI != SignaturesWithConstantForms.end()) {
std::sort(MI->second.begin(), MI->second.end());
MI->second.erase(std::unique(MI->second.begin(), MI->second.end()),
MI->second.end());
-
+
// Check each in order it was seen. It would be nice to have a good
// relative ordering between them, but we're not going for optimality
// here.
MI->second[i].PrintArguments(OS);
OS << "))\n return Reg;\n\n";
}
-
+
// Done with this, remove it.
SignaturesWithConstantForms.erase(MI);
}
-
+
OS << " switch (Opcode) {\n";
for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
I != E; ++I) {
OS << "}\n";
OS << "\n";
}
-
+
// TODO: SignaturesWithConstantForms should be empty here.
}
projects / oota-llvm.git / blobdiff