Remove dead code. Improve llvm_unreachable text. Simplify some control flow.

[oota-llvm.git] / utils / TableGen / EDEmitter.cpp

diff --git a/utils/TableGen/EDEmitter.cpp b/utils/TableGen/EDEmitter.cpp
index 852b9bf125bc5db9bf1926a20bd1e2c35e7c7c82..e0fd566d8db4e36c7a49c5446633c0a525ba5075 100644 (file)
--- a/utils/TableGen/EDEmitter.cpp
+++ b/utils/TableGen/EDEmitter.cpp
@@ -17,8 +17,8 @@
 
 #include "AsmWriterInst.h"
 #include "CodeGenTarget.h"
-#include "Record.h"
 
+#include "llvm/TableGen/Record.h"
 #include "llvm/MC/EDInstInfo.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/Format.h"
@@ -256,12 +256,15 @@ static int X86TypeFromOpName(LiteralConstantEmitter *type,
   REG("GR8");
   REG("GR8_NOREX");
   REG("GR16");
+  REG("GR16_NOAX");
   REG("GR32");
+  REG("GR32_NOAX");
   REG("GR32_NOREX");
   REG("GR32_TC");
   REG("FR32");
   REG("RFP32");
   REG("GR64");
+  REG("GR64_NOAX");
   REG("GR64_TC");
   REG("FR64");
   REG("VR64");
@@ -516,6 +519,8 @@ static void X86ExtractSemantics(
       // ignore (doesn't go anywhere we know about)
     } else if (name.find("VMCALL") != name.npos) {
       // ignore (rather different semantics than a regular call)
+    } else if (name.find("VMMCALL") != name.npos) {
+      // ignore (rather different semantics than a regular call)
     } else if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
       CALL("off");
     } else {
@@ -568,8 +573,18 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
   REG("QPR");
   REG("QQPR");
   REG("QQQQPR");
+  REG("VecListOneD");
+  REG("VecListTwoD");
+  REG("VecListThreeD");
+  REG("VecListFourD");
+  REG("VecListTwoQ");
+  REG("VecListOneDAllLanes");
+  REG("VecListTwoDAllLanes");
+  REG("VecListTwoQAllLanes");
 
   IMM("i32imm");
+  IMM("fbits16");
+  IMM("fbits32");
   IMM("i32imm_hilo16");
   IMM("bf_inv_mask_imm");
   IMM("lsb_pos_imm");
@@ -578,6 +593,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
   IMM("nohash_imm");
   IMM("p_imm");
   IMM("c_imm");
+  IMM("coproc_option_imm");
   IMM("imod_op");
   IMM("iflags_op");
   IMM("cpinst_operand");
@@ -593,6 +609,20 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
   IMM("imm1_16");
   IMM("imm1_32");
   IMM("nModImm");
+  IMM("nImmSplatI8");
+  IMM("nImmSplatI16");
+  IMM("nImmSplatI32");
+  IMM("nImmSplatI64");
+  IMM("nImmVMOVI32");
+  IMM("nImmVMOVF32");
+  IMM("imm8");
+  IMM("imm16");
+  IMM("imm32");
+  IMM("imm1_7");
+  IMM("imm1_15");
+  IMM("imm1_31");
+  IMM("imm0_1");
+  IMM("imm0_3");
   IMM("imm0_7");
   IMM("imm0_15");
   IMM("imm0_255");
@@ -603,12 +633,14 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
   IMM("pkh_lsl_amt");
   IMM("pkh_asr_amt");
   IMM("jt2block_operand");
-  IMM("t_imm_s4");
+  IMM("t_imm0_1020s4");
+  IMM("t_imm0_508s4");
   IMM("pclabel");
   IMM("adrlabel");
   IMM("t_adrlabel");
   IMM("t2adrlabel");
   IMM("shift_imm");
+  IMM("t2_shift_imm");
   IMM("neon_vcvt_imm32");
   IMM("shr_imm8");
   IMM("shr_imm16");
@@ -619,6 +651,9 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
   IMM("postidx_imm8s4");
   IMM("imm_sr");
   IMM("imm1_31");
+  IMM("VectorIndex8");
+  IMM("VectorIndex16");
+  IMM("VectorIndex32");
 
   MISC("brtarget", "kOperandTypeARMBranchTarget");                // ?
   MISC("uncondbrtarget", "kOperandTypeARMBranchTarget");           // ?
@@ -629,6 +664,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
 
   MISC("br_target", "kOperandTypeARMBranchTarget");                // ?
   MISC("bl_target", "kOperandTypeARMBranchTarget");                // ?
+  MISC("blx_target", "kOperandTypeARMBranchTarget");                // ?
 
   MISC("t_bltarget", "kOperandTypeARMBranchTarget");              // ?
   MISC("t_blxtarget", "kOperandTypeARMBranchTarget");             // ?
@@ -664,11 +700,14 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
   MISC("spr_reglist", "kOperandTypeARMSPRRegisterList");          // I, R, ...
   MISC("it_mask", "kOperandTypeThumbITMask");                     // I
   MISC("t2addrmode_reg", "kOperandTypeThumb2AddrModeReg");        // R
+  MISC("t2addrmode_posimm8", "kOperandTypeThumb2AddrModeImm8");   // R, I
+  MISC("t2addrmode_negimm8", "kOperandTypeThumb2AddrModeImm8");   // R, I
   MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8");      // R, I
   MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I
   MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12");    // R, I
   MISC("t2addrmode_so_reg", "kOperandTypeThumb2AddrModeSoReg");   // R, R, I
   MISC("t2addrmode_imm8s4", "kOperandTypeThumb2AddrModeImm8s4");  // R, I
+  MISC("t2addrmode_imm0_1020s4", "kOperandTypeThumb2AddrModeImm8s4");  // R, I
   MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset");
                                                                   // R, I
   MISC("tb_addrmode", "kOperandTypeARMTBAddrMode");               // I
@@ -681,6 +720,8 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
   MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR");           // R, R
   MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP");           // R, I
   MISC("t_addrmode_pc", "kOperandTypeThumbAddrModePC");           // R, I
+  MISC("addrmode_tbb", "kOperandTypeThumbAddrModeRR");            // R, R
+  MISC("addrmode_tbh", "kOperandTypeThumbAddrModeRR");            // R, R
 
   return 1;
 }
@@ -720,7 +761,7 @@ static void ARMPopulateOperands(
       errs() << "Operand type: " << rec.getName() << '\n';
       errs() << "Operand name: " << operandInfo.Name << '\n';
       errs() << "Instruction name: " << inst.TheDef->getName() << '\n';
-      llvm_unreachable("Unhandled type");
+      throw("Unhandled type in EDEmitter");
     }
   }
 }
@@ -788,11 +829,6 @@ static void populateInstInfo(CompoundConstantEmitter &infoArray,
   for (index = 0; index < numInstructions; ++index) {
     const CodeGenInstruction& inst = *numberedInstructions[index];
 
-    // We don't need to do anything for pseudo-instructions, as we'll never
-    // see them here. We'll only see real instructions.
-    if (inst.isPseudo)
-      continue;
-
     CompoundConstantEmitter *infoStruct = new CompoundConstantEmitter;
     infoArray.addEntry(infoStruct);
 
@@ -825,15 +861,20 @@ static void populateInstInfo(CompoundConstantEmitter &infoArray,
 
     unsigned numSyntaxes = 0;
 
-    if (target.getName() == "X86") {
-      X86PopulateOperands(operandTypes, inst);
-      X86ExtractSemantics(*instType, operandFlags, inst);
-      numSyntaxes = 2;
-    }
-    else if (target.getName() == "ARM") {
-      ARMPopulateOperands(operandTypes, inst);
-      ARMExtractSemantics(*instType, operandTypes, operandFlags, inst);
-      numSyntaxes = 1;
+    // We don't need to do anything for pseudo-instructions, as we'll never
+    // see them here. We'll only see real instructions.
+    // We still need to emit null initializers for everything.
+    if (!inst.isPseudo) {
+      if (target.getName() == "X86") {
+        X86PopulateOperands(operandTypes, inst);
+        X86ExtractSemantics(*instType, operandFlags, inst);
+        numSyntaxes = 2;
+      }
+      else if (target.getName() == "ARM") {
+        ARMPopulateOperands(operandTypes, inst);
+        ARMExtractSemantics(*instType, operandTypes, operandFlags, inst);
+        numSyntaxes = 1;
+      }
     }
 
     CompoundConstantEmitter *operandOrderArray = new CompoundConstantEmitter;
@@ -941,11 +982,7 @@ void EDEmitter::run(raw_ostream &o) {
 
   emitCommonEnums(o, i);
 
-  o << "namespace {\n";
-
-  o << "llvm::EDInstInfo instInfo" << target.getName().c_str() << "[] = ";
+  o << "static const llvm::EDInstInfo instInfo" << target.getName() << "[] = ";
   infoArray.emit(o, i);
   o << ";" << "\n";
-
-  o << "}\n";
 }