[ARM] Emit clrex in the expanded cmpxchg fail block.

[oota-llvm.git] / utils / TableGen / CodeGenSchedule.h

diff --git a/utils/TableGen/CodeGenSchedule.h b/utils/TableGen/CodeGenSchedule.h
index fa964cf23d2a060db0f4662011848eed0e87e6fe..e5241b9d5fda67d12716ecd7157ee2cff5ffc295 100644 (file)
--- a/utils/TableGen/CodeGenSchedule.h
+++ b/utils/TableGen/CodeGenSchedule.h
@@ -7,19 +7,19 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file defines structures to encapsulate the machine model as decribed in
+// This file defines structures to encapsulate the machine model as described in
 // the target description.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef CODEGEN_SCHEDULE_H
-#define CODEGEN_SCHEDULE_H
+#ifndef LLVM_UTILS_TABLEGEN_CODEGENSCHEDULE_H
+#define LLVM_UTILS_TABLEGEN_CODEGENSCHEDULE_H
 
-#include "SetTheory.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/SetTheory.h"
 
 namespace llvm {
 
@@ -56,7 +56,7 @@ struct CodeGenSchedRW {
   RecVec Aliases;
 
   CodeGenSchedRW()
-    : Index(0), TheDef(0), IsRead(false), IsAlias(false),
+    : Index(0), TheDef(nullptr), IsRead(false), IsAlias(false),
       HasVariants(false), IsVariadic(false), IsSequence(false) {}
   CodeGenSchedRW(unsigned Idx, Record *Def)
     : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) {
@@ -74,7 +74,7 @@ struct CodeGenSchedRW {
 
   CodeGenSchedRW(unsigned Idx, bool Read, const IdxVec &Seq,
                  const std::string &Name)
-    : Index(Idx), Name(Name), TheDef(0), IsRead(Read), IsAlias(false),
+    : Index(Idx), Name(Name), TheDef(nullptr), IsRead(Read), IsAlias(false),
       HasVariants(false), IsVariadic(false), IsSequence(true), Sequence(Seq) {
     assert(Sequence.size() > 1 && "implied sequence needs >1 RWs");
   }
@@ -142,7 +142,7 @@ struct CodeGenSchedClass {
   // off to join another inferred class.
   RecVec InstRWs;
 
-  CodeGenSchedClass(): Index(0), ItinClassDef(0) {}
+  CodeGenSchedClass(): Index(0), ItinClassDef(nullptr) {}
 
   bool isKeyEqual(Record *IC, const IdxVec &W, const IdxVec &R) {
     return ItinClassDef == IC && Writes == W && Reads == R;
@@ -162,7 +162,7 @@ struct CodeGenSchedClass {
 // ModelName is a unique name used to name an instantiation of MCSchedModel.
 //
 // ModelDef is NULL for inferred Models. This happens when a processor defines
-// an itinerary but no machine model. If the processer defines neither a machine
+// an itinerary but no machine model. If the processor defines neither a machine
 // model nor itinerary, then ModelDef remains pointing to NoModel. NoModel has
 // the special "NoModel" field set to true.
 //
@@ -248,6 +248,28 @@ class CodeGenSchedModels {
 public:
   CodeGenSchedModels(RecordKeeper& RK, const CodeGenTarget &TGT);
 
+  // iterator access to the scheduling classes.
+  typedef std::vector<CodeGenSchedClass>::iterator class_iterator;
+  typedef std::vector<CodeGenSchedClass>::const_iterator const_class_iterator;
+  class_iterator classes_begin() { return SchedClasses.begin(); }
+  const_class_iterator classes_begin() const { return SchedClasses.begin(); }
+  class_iterator classes_end() { return SchedClasses.end(); }
+  const_class_iterator classes_end() const { return SchedClasses.end(); }
+  iterator_range<class_iterator> classes() {
+   return iterator_range<class_iterator>(classes_begin(), classes_end());
+  }
+  iterator_range<const_class_iterator> classes() const {
+   return iterator_range<const_class_iterator>(classes_begin(), classes_end());
+  }
+  iterator_range<class_iterator> explicit_classes() {
+    return iterator_range<class_iterator>(
+        classes_begin(), classes_begin() + NumInstrSchedClasses);
+  }
+  iterator_range<const_class_iterator> explicit_classes() const {
+    return iterator_range<const_class_iterator>(
+        classes_begin(), classes_begin() + NumInstrSchedClasses);
+  }
+
   Record *getModelOrItinDef(Record *ProcDef) const {
     Record *ModelDef = ProcDef->getValueAsDef("SchedModel");
     Record *ItinsDef = ProcDef->getValueAsDef("ProcItin");