Change a very hot piece of code in TableGen's register unit computations to use bit...

[oota-llvm.git] / utils / TableGen / CodeGenRegisters.cpp

diff --git a/utils/TableGen/CodeGenRegisters.cpp b/utils/TableGen/CodeGenRegisters.cpp
index bef8a4b8fa12abbe947b1e0d69c5416ef9fb31b8..1cf260d0ea1e5f74dac41b002bd129a63565dcb5 100644 (file)
--- a/utils/TableGen/CodeGenRegisters.cpp
+++ b/utils/TableGen/CodeGenRegisters.cpp
@@ -17,6 +17,7 @@
 #include "llvm/ADT/IntEqClasses.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/SparseBitVector.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/Support/Debug.h"
@@ -211,12 +212,24 @@ static bool hasRegUnit(CodeGenRegister::RegUnitList &RegUnits, unsigned Unit) {
 // Return true if the RegUnits changed.
 bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) {
   unsigned OldNumUnits = RegUnits.size();
+
+  SparseBitVector<> NewUnits;
+  for (unsigned RU : RegUnits)
+    NewUnits.set(RU);
+
   for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
        I != E; ++I) {
     CodeGenRegister *SR = I->second;
     // Merge the subregister's units into this register's RegUnits.
-    mergeRegUnits(RegUnits, SR->RegUnits);
+    for (unsigned RU : SR->RegUnits)
+      NewUnits.set(RU);
   }
+
+  RegUnits.clear();
+  RegUnits.reserve(NewUnits.count());
+  for (unsigned RU : NewUnits)
+    RegUnits.push_back(RU);
+
   return OldNumUnits != RegUnits.size();
 }