[TableGen] Optionally forbid overlap between named and positional operands

[oota-llvm.git] / utils / TableGen / CodeEmitterGen.cpp

diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp
index b7dea1046ba66d379021e9d04d2510d5c9ff517c..a7fca06cf0fada3d3bd1441a2d86ca026f7dff04 100644 (file)
--- a/utils/TableGen/CodeEmitterGen.cpp
+++ b/utils/TableGen/CodeEmitterGen.cpp
@@ -48,6 +48,7 @@ private:
   void AddCodeToMergeInOperand(Record *R, BitsInit *BI,
                                const std::string &VarName,
                                unsigned &NumberedOp,
+                               std::set<unsigned> &NamedOpIndices,
                                std::string &Case, CodeGenTarget &Target);
 
 };
@@ -71,6 +72,7 @@ int CodeEmitterGen::getVariableBit(const std::string &VarName,
 void CodeEmitterGen::
 AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName,
                         unsigned &NumberedOp,
+                        std::set<unsigned> &NamedOpIndices,
                         std::string &Case, CodeGenTarget &Target) {
   CodeGenInstruction &CGI = Target.getInstruction(R);
 
@@ -103,7 +105,9 @@ AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName,
     /// If this operand is not supposed to be emitted by the
     /// generated emitter, skip it.
     while (NumberedOp < NumberOps &&
-           CGI.Operands.isFlatOperandNotEmitted(NumberedOp))
+           (CGI.Operands.isFlatOperandNotEmitted(NumberedOp) ||
+              (NamedOpIndices.size() && NamedOpIndices.count(
+                CGI.Operands.getSubOperandNumber(NumberedOp).first))))
       ++NumberedOp;
 
     OpIdx = NumberedOp++;
@@ -122,14 +126,14 @@ AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName,
       Case += "      // op: " + VarName + "\n" +
               "      op = " + EncoderMethodName + "(MI, " + utostr(OpIdx);
       if (MCEmitter)
-        Case += ", Fixups";
+        Case += ", Fixups, STI";
       Case += ");\n";
     }
   } else {
     Case += "      // op: " + VarName + "\n" +
       "      op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
     if (MCEmitter)
-      Case += ", Fixups";
+      Case += ", Fixups, STI";
     Case += ");\n";
   }
   
@@ -180,6 +184,21 @@ std::string CodeEmitterGen::getInstructionCase(Record *R,
   const std::vector<RecordVal> &Vals = R->getValues();
   unsigned NumberedOp = 0;
 
+  std::set<unsigned> NamedOpIndices;
+  // Collect the set of operand indices that might correspond to named
+  // operand, and skip these when assigning operands based on position.
+  if (Target.getInstructionSet()->
+       getValueAsBit("noNamedPositionallyEncodedOperands")) {
+    CodeGenInstruction &CGI = Target.getInstruction(R);
+    for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
+      unsigned OpIdx;
+      if (!CGI.Operands.hasOperandNamed(Vals[i].getName(), OpIdx))
+        continue;
+
+      NamedOpIndices.insert(OpIdx);
+    }
+  }
+
   // Loop over all of the fields in the instruction, determining which are the
   // operands to the instruction.
   for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
@@ -188,12 +207,17 @@ std::string CodeEmitterGen::getInstructionCase(Record *R,
     if (Vals[i].getPrefix() || Vals[i].getValue()->isComplete())
       continue;
     
-    AddCodeToMergeInOperand(R, BI, Vals[i].getName(), NumberedOp, Case, Target);
+    AddCodeToMergeInOperand(R, BI, Vals[i].getName(), NumberedOp,
+                            NamedOpIndices, Case, Target);
   }
   
   std::string PostEmitter = R->getValueAsString("PostEncoderMethod");
-  if (!PostEmitter.empty())
-    Case += "      Value = " + PostEmitter + "(MI, Value);\n";
+  if (!PostEmitter.empty()) {
+    Case += "      Value = " + PostEmitter + "(MI, Value";
+    if (MCEmitter)
+      Case += ", STI";
+    Case += ");\n";
+  }
   
   return Case;
 }
@@ -212,7 +236,8 @@ void CodeEmitterGen::run(raw_ostream &o) {
   o << "uint64_t " << Target.getName();
   if (MCEmitter)
     o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n"
-      << "    SmallVectorImpl<MCFixup> &Fixups) const {\n";
+      << "    SmallVectorImpl<MCFixup> &Fixups,\n"
+      << "    const MCSubtargetInfo &STI) const {\n";
   else
     o << "CodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) const {\n";