Removed colons from some target datalayout strings in test, since they don't match...

[oota-llvm.git] / test / Transforms / LoopSimplify / single-backedge.ll

diff --git a/test/Transforms/LoopSimplify/single-backedge.ll b/test/Transforms/LoopSimplify/single-backedge.ll
index 53a6ffbf9823d2f516a265df7f32974db5ee0213..aedd6f23091c92d01ab8f3593b982521b7902d8b 100644 (file)
--- a/test/Transforms/LoopSimplify/single-backedge.ll
+++ b/test/Transforms/LoopSimplify/single-backedge.ll
@@ -1,17 +1,23 @@
-; The loop canonicalization pass should guarantee that there is one backedge 
-; for all loops.  This allows the -indvars pass to recognize the %IV 
+; The loop canonicalization pass should guarantee that there is one backedge
+; for all loops.  This allows the -indvars pass to recognize the %IV
 ; induction variable in this testcase.
 
-; RUN: llvm-upgrade < %s | llvm-as | opt -indvars | llvm-dis | grep indvar
+; RUN: opt < %s -indvars -S | FileCheck %s
+; CHECK: Loop.backedge:
+; CHECK-NOT: br
+; CHECK: br label %Loop
 
-int %test(bool %C) {
+define i32 @test(i1 %C) {
+; <label>:0
        br label %Loop
-Loop:
-       %IV = phi uint [1, %0], [%IV2, %BE1], [%IV2, %BE2]
-       %IV2 = add uint %IV, 2
-       br bool %C, label %BE1, label %BE2
-BE1:
+Loop:          ; preds = %BE2, %BE1, %0
+       %IV = phi i32 [ 1, %0 ], [ %IV2, %BE1 ], [ %IV2, %BE2 ]         ; <i32> [#uses=2]
+       store i32 %IV, i32* null
+       %IV2 = add i32 %IV, 2           ; <i32> [#uses=2]
+       br i1 %C, label %BE1, label %BE2
+BE1:           ; preds = %Loop
        br label %Loop
-BE2:
+BE2:           ; preds = %Loop
        br label %Loop
 }
+