Verifier: Call verifyModule() from llc and opt

[oota-llvm.git] / test / Transforms / InstCombine / vec_phi_extract.ll

diff --git a/test/Transforms/InstCombine/vec_phi_extract.ll b/test/Transforms/InstCombine/vec_phi_extract.ll
index b0f365ba79648d06dddd530fc8e691e528799ef6..1079dc9e719897e9f8655a648fb8a0de5026882c 100644 (file)
--- a/test/Transforms/InstCombine/vec_phi_extract.ll
+++ b/test/Transforms/InstCombine/vec_phi_extract.ll
@@ -16,7 +16,7 @@ loop:
   %end = icmp ult i32 %elt, %limit
   %3 = add i32 10, %elt
   %4 = sext i32 %elt to i64
-  %5 = getelementptr i32* %ptr, i64 %4
+  %5 = getelementptr i32, i32* %ptr, i64 %4
   store i32 %3, i32* %5
   %inc = add <16 x i32> %2, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
   br i1 %end, label %loop, label %ret
@@ -39,7 +39,7 @@ for.cond:
 ; CHECK: extractelement
 for.body:
   %dec43 = add <3 x i32> %input_1.addr.1, <i32 -1, i32 -1, i32 -1>
-  %sub44 = sub <3 x i32> zeroinitializer, %dec43
+  %sub44 = sub <3 x i32> <i32 -1, i32 -1, i32 -1>, %dec43
   %div45 = sdiv <3 x i32> %input_2.addr.0, %sub44
   br label %for.cond