Address issues found by Duncan during post-commit review of r177856.

[oota-llvm.git] / test / Transforms / InstCombine / trunc.ll

diff --git a/test/Transforms/InstCombine/trunc.ll b/test/Transforms/InstCombine/trunc.ll
index 5cb34746676b4d90dd889ed8383841d6a63d173e..cbbad7f797770a8d0c57b47975ce7a3d73e14957 100644 (file)
--- a/test/Transforms/InstCombine/trunc.ll
+++ b/test/Transforms/InstCombine/trunc.ll
@@ -1,4 +1,5 @@
 ; RUN: opt < %s -instcombine -S | FileCheck %s
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 
 ; Instcombine should be able to eliminate all of these ext casts.
 
@@ -11,8 +12,8 @@ define i64 @test1(i64 %a) {
   call void @use(i32 %b)
   ret i64 %d
 ; CHECK: @test1
-; CHECK: %d = and i64 %a, 15
-; CHECK: ret i64 %d
+; CHECK-NOT: ext
+; CHECK: ret
 }
 define i64 @test2(i64 %a) {
   %b = trunc i64 %a to i32
@@ -23,7 +24,7 @@ define i64 @test2(i64 %a) {
   ret i64 %d
 ; CHECK: @test2
 ; CHECK: shl i64 %a, 36
-; CHECK: %d = ashr i64 {{.*}}, 36
+; CHECK: %d = ashr exact i64 {{.*}}, 36
 ; CHECK: ret i64 %d
 }
 define i64 @test3(i64 %a) {
@@ -33,8 +34,8 @@ define i64 @test3(i64 %a) {
   call void @use(i32 %b)
   ret i64 %d
 ; CHECK: @test3
-; CHECK: %d = and i64 %a, 8
-; CHECK: ret i64 %d
+; CHECK-NOT: ext
+; CHECK: ret
 }
 define i64 @test4(i64 %a) {
   %b = trunc i64 %a to i32
@@ -45,8 +46,9 @@ define i64 @test4(i64 %a) {
   ret i64 %d
 ; CHECK: @test4
 ; CHECK: = and i64 %a, 8
-; CHECK: %d = xor i64 {{.*}}, 8
-; CHECK: ret i64 %d
+; CHECK: = xor i64 {{.*}}, 8
+; CHECK-NOT: ext
+; CHECK: ret
 }
 
 define i32 @test5(i32 %A) {
@@ -76,7 +78,43 @@ define i92 @test7(i64 %A) {
   %D = trunc i128 %C to i92
   ret i92 %D
 ; CHECK: @test7
-; CHECK: %C = lshr i64 %A, 32
-; CHECK: %D = zext i64 %C to i92
-; CHECK: ret i92 %D
-}
\ No newline at end of file
+; CHECK: %B = zext i64 %A to i92
+; CHECK: %C = lshr i92 %B, 32
+; CHECK: ret i92 %C
+}
+
+define i64 @test8(i32 %A, i32 %B) {
+  %tmp38 = zext i32 %A to i128
+  %tmp32 = zext i32 %B to i128
+  %tmp33 = shl i128 %tmp32, 32
+  %ins35 = or i128 %tmp33, %tmp38
+  %tmp42 = trunc i128 %ins35 to i64
+  ret i64 %tmp42
+; CHECK: @test8
+; CHECK:   %tmp38 = zext i32 %A to i64
+; CHECK:   %tmp32 = zext i32 %B to i64
+; CHECK:   %tmp33 = shl nuw i64 %tmp32, 32
+; CHECK:   %ins35 = or i64 %tmp33, %tmp38
+; CHECK:   ret i64 %ins35
+}
+
+define i8 @test9(i32 %X) {
+  %Y = and i32 %X, 42
+  %Z = trunc i32 %Y to i8
+  ret i8 %Z
+; CHECK: @test9
+; CHECK: trunc
+; CHECK: and
+; CHECK: ret
+}
+
+; rdar://8808586
+define i8 @test10(i32 %X) {
+  %Y = trunc i32 %X to i8
+  %Z = and i8 %Y, 42
+  ret i8 %Z
+; CHECK: @test10
+; CHECK: trunc
+; CHECK: and
+; CHECK: ret
+}