[Hexagon] Updating predicate register transfers and adding tstbit to allow select...
[oota-llvm.git] / test / MC / Hexagon / inst_select.ll
index c3a11082f5fa6ee75fc544a1cb9e20a8a0bb868b..7e88c65a81852c9290e31aa998a8ae60fa503b1c 100644 (file)
@@ -7,4 +7,4 @@ define i32 @foo (i1 %a, i32 %b, i32 %c)
   ret i32 %1
 }
 
-; CHECK:  0000 00400000 004201f4 00c09f52
+; CHECK:  0000 00400085 004201f4 00c09f52