[Hexagon] Updating predicate register transfers and adding tstbit to allow select...

[oota-llvm.git] / test / MC / Hexagon / inst_cmp_ult.ll

diff --git a/test/MC/Hexagon/inst_cmp_ult.ll b/test/MC/Hexagon/inst_cmp_ult.ll
index 8811767aff08088d5db13871ed6e45551d8c0d65..4323fa0834d67dd0be4c5715b2b371eba1a25f84 100644 (file)
--- a/test/MC/Hexagon/inst_cmp_ult.ll
+++ b/test/MC/Hexagon/inst_cmp_ult.ll
@@ -7,4 +7,4 @@ define i1 @foo (i32 %a, i32 %b)
   ret i1 %1
 }
 
-; CHECK:  0000 004061f2 00400000 00c09f52
+; CHECK:  0000 004061f2 00404089 00c09f52