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[Hexagon] Updating predicate register transfers and adding tstbit to allow select...
[oota-llvm.git]
/
test
/
MC
/
Hexagon
/
inst_cmp_eq.ll
diff --git
a/test/MC/Hexagon/inst_cmp_eq.ll
b/test/MC/Hexagon/inst_cmp_eq.ll
index 1904cf336169cc48ec4cd22ddcd2d5efad4369fc..113db631fa92f2069c1427169160776a1a3ea9db 100644
(file)
--- a/
test/MC/Hexagon/inst_cmp_eq.ll
+++ b/
test/MC/Hexagon/inst_cmp_eq.ll
@@
-7,4
+7,4
@@
define i1 @foo (i32 %a, i32 %b)
ret i1 %1
}
-; CHECK: 0000 004100f2 0040
0000
00c09f52
+; CHECK: 0000 004100f2 0040
4089
00c09f52