Add instruction encodings / disassembler support for 2rus instructions.

[oota-llvm.git] / test / MC / Disassembler / XCore / xcore.txt

diff --git a/test/MC/Disassembler/XCore/xcore.txt b/test/MC/Disassembler/XCore/xcore.txt
index b022f502313a64cd892118ae37f28962e6d33135..5b7b37538426bc1b7ccd7abf6baa107c07c9d289 100644 (file)
--- a/test/MC/Disassembler/XCore/xcore.txt
+++ b/test/MC/Disassembler/XCore/xcore.txt
@@ -234,3 +234,26 @@
 
 # CHECK: sub r4, r2, r5
 0x89 0x1a
+
+# 2rus instructions
+
+# CHECK: add r10, r2, 5
+0xe9 0x92
+
+# CHECK: eq r2, r1, 0
+0x24 0xb0
+
+# CHECK: ldw r5, r6[1]
+0x19 0x09
+
+# CHECK: shl r6, r5, 24
+0xa6 0xa5
+
+# CHECK: shr r3, r8, 5
+0xf1 0xab
+
+# CHECK: stw r3, r2[0]
+0x38 0x00
+
+# CHECK: sub r2, r4, 11
+0x63 0x9d