Add instruction encodings / disassembly support for 0r instructions.

[oota-llvm.git] / test / MC / Disassembler / XCore / xcore.txt

diff --git a/test/MC/Disassembler/XCore/xcore.txt b/test/MC/Disassembler/XCore/xcore.txt
index 3dacf6d3b63a1f2d3a08c593adea29b1728dbff9..45060c678ec5c29b66a6805e42da56ab5d790235 100644 (file)
--- a/test/MC/Disassembler/XCore/xcore.txt
+++ b/test/MC/Disassembler/XCore/xcore.txt
@@ -1,6 +1,26 @@
 # RUN: llvm-mc --disassemble %s -triple=xcore-xmos-elf | FileCheck %s
 # CHECK: .section        __TEXT,__text,regular,pure_instructions
 
+# 0r instructions
+
+# CHECK: clre
+0xed 0x07
+
+# CHECK: get r11, id
+0xee 0x17
+
+# CHECK: get r11, ed
+0xfe 0x0f
+
+# CHECK: get r11, et
+0xff 0x0f
+
+# CHECK: ssync
+0xee 0x07
+
+# CHECK: waiteu
+0xec 0x07
+
 # 1r instructions
 
 # CHECK: msync res[r0]