[mips][microMIPS] Implement TEQ, TGE, TGEU, TLT, TLTU and TNE instructions

[oota-llvm.git] / test / MC / Disassembler / Mips / micromips64r6.txt

diff --git a/test/MC/Disassembler/Mips/micromips64r6.txt b/test/MC/Disassembler/Mips/micromips64r6.txt
index 1feeca16bea92ce79a4573f96725e98197040cd1..0f8469c4c833e11fd12ac9fce4668cc17779af77 100644 (file)
--- a/test/MC/Disassembler/Mips/micromips64r6.txt
+++ b/test/MC/Disassembler/Mips/micromips64r6.txt
@@ -225,3 +225,27 @@
 0x09 0x94 # CHECK: lbu16 $3, 4($17)
 
 0x09 0x9f # CHECK: lbu16 $3, -1($17)
+
+0x01 0x28 0x00 0x3c # CHECK: teq $8, $9
+
+0x00 0xe5 0xf0 0x3c # CHECK: teq $5, $7, 15
+
+0x01 0x47 0x02 0x3c # CHECK: tge $7, $10
+
+0x02 0x67 0xf2 0x3c # CHECK: tge $7, $19, 15
+
+0x03 0x96 0x04 0x3c # CHECK: tgeu $22, $gp
+
+0x01 0xd4 0xf4 0x3c # CHECK: tgeu $20, $14, 15
+
+0x01 0xaf 0x08 0x3c # CHECK: tlt $15, $13
+
+0x02 0x62 0xf8 0x3c # CHECK: tlt $2, $19, 15
+
+0x02 0x0b 0x0a 0x3c # CHECK: tltu $11, $16
+
+0x03 0xb0 0xfa 0x3c # CHECK: tltu $16, $sp, 15
+
+0x02 0x26 0x0c 0x3c # CHECK: tne $6, $17
+
+0x01 0x07 0xfc 0x3c # CHECK: tne $7, $8, 15