[mips][microMIPS] Implement TEQ, TGE, TGEU, TLT, TLTU and TNE instructions

[oota-llvm.git] / test / MC / Disassembler / Mips / micromips32r6.txt

diff --git a/test/MC/Disassembler/Mips/micromips32r6.txt b/test/MC/Disassembler/Mips/micromips32r6.txt
index 43debbe4acf07a6a693f8fc7cb6695a83f74354c..fe28c3d281b27b72a3de6b33729ce6261c96657a 100644 (file)
--- a/test/MC/Disassembler/Mips/micromips32r6.txt
+++ b/test/MC/Disassembler/Mips/micromips32r6.txt
@@ -355,3 +355,27 @@
 0x60 0x25 0xa6 0x08 # CHECK: cachee 1, 8($5)
 
 0x60 0x25 0xa4 0x08 # CHECK: prefe 1, 8($5)
+
+0x01 0x28 0x00 0x3c # CHECK: teq $8, $9
+
+0x00 0xe5 0xf0 0x3c # CHECK: teq $5, $7, 15
+
+0x01 0x47 0x02 0x3c # CHECK: tge $7, $10
+
+0x02 0x67 0xf2 0x3c # CHECK: tge $7, $19, 15
+
+0x03 0x96 0x04 0x3c # CHECK: tgeu $22, $gp
+
+0x01 0xd4 0xf4 0x3c # CHECK: tgeu $20, $14, 15
+
+0x01 0xaf 0x08 0x3c # CHECK: tlt $15, $13
+
+0x02 0x62 0xf8 0x3c # CHECK: tlt $2, $19, 15
+
+0x02 0x0b 0x0a 0x3c # CHECK: tltu $11, $16
+
+0x03 0xb0 0xfa 0x3c # CHECK: tltu $16, $sp, 15
+
+0x02 0x26 0x0c 0x3c # CHECK: tne $6, $17
+
+0x01 0x07 0xfc 0x3c # CHECK: tne $7, $8, 15