[mips][microMIPSr6] Implement NOR, OR, ORI, XOR and XORI instructions

[oota-llvm.git] / test / MC / Disassembler / Mips / micromips32r6.txt

diff --git a/test/MC/Disassembler/Mips/micromips32r6.txt b/test/MC/Disassembler/Mips/micromips32r6.txt
index 0d840e4a4ea403aa0a31b82393af292b5d5ddc6b..7118d704fd106623002209154a1c615ac3e38cdd 100644 (file)
--- a/test/MC/Disassembler/Mips/micromips32r6.txt
+++ b/test/MC/Disassembler/Mips/micromips32r6.txt
@@ -12,6 +12,14 @@
 
 0x78 0x7e 0xff 0xff # CHECK: auipc $3, -1
 
+0x00 0x43 0x24 0x1f # CHECK: align $4, $2, $3, 2
+
+0x00 0xa4 0x1a 0x50 # CHECK: and $3, $4, $5
+
+0xd0 0x64 0x04 0xd2 # CHECK: andi $3, $4, 1234
+
+0x10 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23
+
 # CHECK: balc 14572256
 0xb4 0x37 0x96 0xb8
 
@@ -24,12 +32,26 @@
 # CHECK: cache 1, 8($5)
 0x20 0x25 0x60 0x08
 
+0x01 0x65 0x4b 0x3c # CHECK: clo $11, $5
+
+0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp
+
+0x00 0xa4 0x19 0x18 # CHECK: div $3, $4, $5
+
+0x00 0xa4 0x19 0x98 # CHECK: divu $3, $4, $5
+
 0x80 0x05 0x01 0x00 # CHECK: jialc $5, 256
 
 0xa0 0x05 0x01 0x00 # CHECK: jic $5, 256
 
 0x78 0x48 0x00 0x43 # CHECK: lwpc $2, 268
 
+0x00 0x43 0x26 0x0f # CHECK: lsa $2, $3, $4, 3
+
+0x00 0xa4 0x19 0x58 # CHECK: mod $3, $4, $5
+
+0x00 0xa4 0x19 0xd8 # CHECK: modu $3, $4, $5
+
 0x00 0xa4 0x18 0x18 # CHECK: mul $3, $4, $5
 
 0x00 0xa4 0x18 0x58 # CHECK: muh $3, $4, $5
@@ -38,10 +60,24 @@
 
 0x00 0xa4,0x18,0xd8 # CHECK: muhu $3, $4, $5
 
+0x00 0xa4 0x1a 0xd0 # CHECK: nor $3, $4, $5
+
+0x00,0xa4,0x1a,0x90 # CHECK: or $3, $4, $5
+
+0x50 0x64 0x04 0xd2 # CHECK: ori $3, $4, 1234
+
 # CHECK: pref 1, 8($5)
 0x60 0x25 0x20 0x08
 
+0x00 0x83 0x11 0x40 # CHECK: seleqz $2, $3, $4
+
+0x00 0x83 0x11 0x80 # CHECK: selnez $2, $3, $4
+
 0x00 0xa4 0x19 0x90 # CHECK: sub $3, $4, $5
 
 0x00 0xa4 0x19 0xd0 # CHECK: subu $3, $4, $5
 
+0x00 0xa4 0x1b 0x10 # CHECK: xor $3, $4, $5
+
+0x70 0x64 0x04 0xd2 # CHECK: xori $3, $4, 1234
+