[Hexagon] Adding vector shift instructions and tests.

[oota-llvm.git] / test / MC / Disassembler / Hexagon / xtype_shift.txt

diff --git a/test/MC/Disassembler/Hexagon/xtype_shift.txt b/test/MC/Disassembler/Hexagon/xtype_shift.txt
index a0577383d80e6eeb158e497cb376b19592b4a450..e2d6816c1cac769fd7a9c5cdcb791cb05de18547 100644 (file)
--- a/test/MC/Disassembler/Hexagon/xtype_shift.txt
+++ b/test/MC/Disassembler/Hexagon/xtype_shift.txt
@@ -1,5 +1,7 @@
-# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.10.8 XTYPE/SHIFT
 
+# Shift by immediate
 0x10 0xdf 0x14 0x80
 # CHECK: r17:16 = asr(r21:20, #31)
 0x30 0xdf 0x14 0x80
@@ -12,6 +14,8 @@
 # CHECK: r17 = lsr(r21, #31)
 0x51 0xdf 0x15 0x8c
 # CHECK: r17 = asl(r21, #31)
+
+# Shift by immediate and accumulate
 0x10 0xdf 0x14 0x82
 # CHECK: r17:16 -= asr(r21:20, #31)
 0x30 0xdf 0x14 0x82
@@ -44,8 +48,12 @@
 # CHECK: r17 = add(#21, lsr(r17, #23))
 0x5e 0xf7 0x11 0xde
 # CHECK: r17 = sub(#21, lsr(r17, #23))
+
+# Shift by immediate and add
 0xf1 0xd5 0x1f 0xc4
 # CHECK: r17 = addasl(r21, r31, #7)
+
+# Shift by immediate and logical
 0x10 0xdf 0x54 0x82
 # CHECK: r17:16 &= asr(r21:20, #31)
 0x30 0xdf 0x54 0x82
@@ -62,18 +70,6 @@
 # CHECK: r17:16 ^= lsr(r21:20, #31)
 0x50 0xdf 0x94 0x82
 # CHECK: r17:16 ^= asl(r21:20, #31)
-0x48 0xff 0x11 0xde
-# CHECK: r17 = and(#21, asl(r17, #31))
-0x4a 0xff 0x11 0xde
-# CHECK: r17 = or(#21, asl(r17, #31))
-0x58 0xff 0x11 0xde
-# CHECK: r17 = and(#21, lsr(r17, #31))
-0x5a 0xff 0x11 0xde
-# CHECK: r17 = or(#21, lsr(r17, #31))
-0xf0 0xdf 0xd4 0x80
-# CHECK: r17:16 = asr(r21:20, #31):rnd
-0x11 0xdf 0x55 0x8c
-# CHECK: r17 = asr(r21, #31):rnd
 0x11 0xdf 0x55 0x8e
 # CHECK: r17 &= asr(r21, #31)
 0x31 0xdf 0x55 0x8e
@@ -90,12 +86,26 @@
 # CHECK: r17 ^= lsr(r21, #31)
 0x51 0xdf 0x95 0x8e
 # CHECK: r17 ^= asl(r21, #31)
+0x48 0xff 0x11 0xde
+# CHECK: r17 = and(#21, asl(r17, #31))
+0x4a 0xff 0x11 0xde
+# CHECK: r17 = or(#21, asl(r17, #31))
+0x58 0xff 0x11 0xde
+# CHECK: r17 = and(#21, lsr(r17, #31))
+0x5a 0xff 0x11 0xde
+# CHECK: r17 = or(#21, lsr(r17, #31))
+
+# Shift right by immediate with rounding
 0xf0 0xdf 0xd4 0x80
 # CHECK: r17:16 = asr(r21:20, #31):rnd
 0x11 0xdf 0x55 0x8c
 # CHECK: r17 = asr(r21, #31):rnd
+
+# Shift left by immediate with saturation
 0x51 0xdf 0x55 0x8c
 # CHECK: r17 = asl(r21, #31):sat
+
+# Shift by register
 0x10 0xdf 0x94 0xc3
 # CHECK: r17:16 = asr(r21:20, r31)
 0x50 0xdf 0x94 0xc3
@@ -114,6 +124,8 @@
 # CHECK: r17 = lsl(r21, r31)
 0xf1 0xdf 0x8a 0xc6
 # CHECK: r17 = lsl(#21, r31)
+
+# Shift by register and accumulate
 0x10 0xdf 0x94 0xcb
 # CHECK: r17:16 -= asr(r21:20, r31)
 0x50 0xdf 0x94 0xcb
@@ -146,6 +158,8 @@
 # CHECK: r17 += asl(r21, r31)
 0xd1 0xdf 0xd5 0xcc
 # CHECK: r17 += lsl(r21, r31)
+
+# Shift by register and logical
 0x10 0xdf 0x14 0xcb
 # CHECK: r17:16 |= asr(r21:20, r31)
 0x50 0xdf 0x14 0xcb
@@ -186,7 +200,61 @@
 # CHECK: r17 &= asl(r21, r31)
 0xd1 0xdf 0x55 0xcc
 # CHECK: r17 &= lsl(r21, r31)
+
+# Shift by register with saturation
 0x11 0xdf 0x15 0xc6
 # CHECK: r17 = asr(r21, r31):sat
 0x91 0xdf 0x15 0xc6
 # CHECK: r17 = asl(r21, r31):sat
+
+# Vector shift halfwords by immediate
+0x10 0xc5 0x94 0x80
+# CHECK: r17:16 = vasrh(r21:20, #5)
+0x30 0xc5 0x94 0x80
+# CHECK: r17:16 = vlsrh(r21:20, #5)
+0x50 0xc5 0x94 0x80
+# CHECK: r17:16 = vaslh(r21:20, #5)
+
+# Vector arithmetic shift halfwords with round
+0x10 0xc5 0x34 0x80
+# CHECK: r17:16 = vasrh(r21:20, #5):raw
+
+# Vector arithmetic shift halfwords with saturate and pack
+0x91 0xc5 0x74 0x88
+# CHECK: r17 = vasrhub(r21:20, #5):raw
+0xb1 0xc5 0x74 0x88
+# CHECK: r17 = vasrhub(r21:20, #5):sat
+
+# Vector shift halfwords by register
+0x10 0xdf 0x54 0xc3
+# CHECK: r17:16 = vasrh(r21:20, r31)
+0x50 0xdf 0x54 0xc3
+# CHECK: r17:16 = vlsrh(r21:20, r31)
+0x90 0xdf 0x54 0xc3
+# CHECK: r17:16 = vaslh(r21:20, r31)
+0xd0 0xdf 0x54 0xc3
+# CHECK: r17:16 = vlslh(r21:20, r31)
+
+# Vector shift words by immediate
+0x10 0xdf 0x54 0x80
+# CHECK: r17:16 = vasrw(r21:20, #31)
+0x30 0xdf 0x54 0x80
+# CHECK: r17:16 = vlsrw(r21:20, #31)
+0x50 0xdf 0x54 0x80
+# CHECK: r17:16 = vaslw(r21:20, #31)
+
+# Vector shift words by register
+0x10 0xdf 0x14 0xc3
+# CHECK: r17:16 = vasrw(r21:20, r31)
+0x50 0xdf 0x14 0xc3
+# CHECK: r17:16 = vlsrw(r21:20, r31)
+0x90 0xdf 0x14 0xc3
+# CHECK: r17:16 = vaslw(r21:20, r31)
+0xd0 0xdf 0x14 0xc3
+# CHECK: r17:16 = vlslw(r21:20, r31)
+
+# Vector shift words with truncate and pack
+0x51 0xdf 0xd4 0x88
+# CHECK: r17 = vasrw(r21:20, #31)
+0x51 0xdf 0x14 0xc5
+# CHECK: r17 = vasrw(r21:20, r31)