[Hexagon] Adding missing instruction encodings and tests.

[oota-llvm.git] / test / MC / Disassembler / Hexagon / alu32_perm.txt

diff --git a/test/MC/Disassembler/Hexagon/alu32_perm.txt b/test/MC/Disassembler/Hexagon/alu32_perm.txt
index 15977edbd6b73a25fb98586a0837d74c7265fb34..98a5d3010077a69505d6704d8fd1009030ea7665 100644 (file)
--- a/test/MC/Disassembler/Hexagon/alu32_perm.txt
+++ b/test/MC/Disassembler/Hexagon/alu32_perm.txt
@@ -1,5 +1,7 @@
 # RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.1.2 ALU32/PERM
 
+# Combine words in to doublewords
 0x11 0xdf 0x95 0xf3
 # CHECK: r17 = combine(r31.h, r21.h)
 0x11 0xdf 0xb5 0xf3
@@ -16,6 +18,8 @@
 # CHECK: r17:16 = combine(r21, #31)
 0x10 0xdf 0x15 0xf5
 # CHECK: r17:16 = combine(r21, r31)
+
+# Mux
 0xf1 0xc3 0x75 0x73
 # CHECK: r17 = mux(p3, r21, #31)
 0xb1 0xc2 0xff 0x73
@@ -24,9 +28,13 @@
 # CHECK: r17 = mux(p3, #21, #31)
 0x71 0xdf 0x15 0xf4
 # CHECK: r17 = mux(p3, r21, r31)
+
+# Shift word by 16
 0x11 0xc0 0x15 0x70
 # CHECK: r17 = aslh(r21)
 0x11 0xc0 0x35 0x70
 # CHECK: r17 = asrh(r21)
+
+# Pack high and low halfwords
 0x10 0xdf 0x95 0xf5
 # CHECK: r17:16 = packhl(r21, r31)