--- /dev/null
+# RUN: not llvm-mc -disassemble -triple thumbv8a-none-eabi -mattr=+fullfp16,+neon,+thumb-mode -show-encoding < %s 2>%t | FileCheck %s
+# RUN FileCheck %s < %t --check-prefix=STDERR
+
+# CHECK: vadd.f16 d0, d1, d2
+# CHECK: vadd.f16 q0, q1, q2
+[0x11,0xef,0x02,0x0d]
+[0x12,0xef,0x44,0x0d]
+
+# CHECK: vsub.f16 d0, d1, d2
+# CHECK: vsub.f16 q0, q1, q2
+[0x31,0xef,0x02,0x0d]
+[0x32,0xef,0x44,0x0d]
+
+# CHECK: vmul.f16 d0, d1, d2
+# CHECK: vmul.f16 q0, q1, q2
+[0x11,0xff,0x12,0x0d]
+[0x12,0xff,0x54,0x0d]
+
+# CHECK: vmul.f16 d1, d2, d3[2]
+# CHECK: vmul.f16 q4, q5, d6[3]
+[0x92,0xef,0x63,0x19]
+[0x9a,0xff,0x6e,0x89]
+
+# CHECK: vmla.f16 d0, d1, d2
+# CHECK: vmla.f16 q0, q1, q2
+[0x11,0xef,0x12,0x0d]
+[0x12,0xef,0x54,0x0d]
+
+# CHECK: vmla.f16 d5, d6, d7[2]
+# CHECK: vmla.f16 q5, q6, d7[3]
+[0x96,0xef,0x67,0x51]
+[0x9c,0xff,0x6f,0xa1]
+
+# CHECK: vmls.f16 d0, d1, d2
+# CHECK: vmls.f16 q0, q1, q2
+[0x31,0xef,0x12,0x0d]
+[0x32,0xef,0x54,0x0d]
+
+# CHECK: vmls.f16 d5, d6, d7[2]
+# CHECK: vmls.f16 q5, q6, d7[3]
+[0x96,0xef,0x67,0x55]
+[0x9c,0xff,0x6f,0xa5]
+
+# CHECK: vfma.f16 d0, d1, d2
+# CHECK: vfma.f16 q0, q1, q2
+[0x11,0xef,0x12,0x0c]
+[0x12,0xef,0x54,0x0c]
+
+# CHECK: vfms.f16 d0, d1, d2
+# CHECK: vfms.f16 q0, q1, q2
+[0x31,0xef,0x12,0x0c]
+[0x32,0xef,0x54,0x0c]
+
+# CHECK: vceq.f16 d2, d3, d4
+# CHECK: vceq.f16 q2, q3, q4
+[0x13,0xef,0x04,0x2e]
+[0x16,0xef,0x48,0x4e]
+
+# CHECK: vceq.f16 d2, d3, #0
+# CHECK: vceq.f16 q2, q3, #0
+[0xb5,0xff,0x03,0x25]
+[0xb5,0xff,0x46,0x45]
+
+# CHECK: vcge.f16 d2, d3, d4
+# CHECK: vcge.f16 q2, q3, q4
+[0x13,0xff,0x04,0x2e]
+[0x16,0xff,0x48,0x4e]
+
+# CHECK: vcge.f16 d2, d3, #0
+# CHECK: vcge.f16 q2, q3, #0
+[0xb5,0xff,0x83,0x24]
+[0xb5,0xff,0xc6,0x44]
+
+# CHECK: vcgt.f16 d2, d3, d4
+# CHECK: vcgt.f16 q2, q3, q4
+[0x33,0xff,0x04,0x2e]
+[0x36,0xff,0x48,0x4e]
+
+# CHECK: vcgt.f16 d2, d3, #0
+# CHECK: vcgt.f16 q2, q3, #0
+[0xb5,0xff,0x03,0x24]
+[0xb5,0xff,0x46,0x44]
+
+# CHECK: vcle.f16 d2, d3, #0
+# CHECK: vcle.f16 q2, q3, #0
+[0xb5,0xff,0x83,0x25]
+[0xb5,0xff,0xc6,0x45]
+
+# CHECK: vclt.f16 d2, d3, #0
+# CHECK: vclt.f16 q2, q3, #0
+[0xb5,0xff,0x03,0x26]
+[0xb5,0xff,0x46,0x46]
+
+# CHECK: vacge.f16 d0, d1, d2
+# CHECK: vacge.f16 q0, q1, q2
+[0x11,0xff,0x12,0x0e]
+[0x12,0xff,0x54,0x0e]
+
+# CHECK: vacgt.f16 d0, d1, d2
+# CHECK: vacgt.f16 q0, q1, q2
+[0x31,0xff,0x12,0x0e]
+[0x32,0xff,0x54,0x0e]
+
+# CHECK: vabd.f16 d0, d1, d2
+# CHECK: vabd.f16 q0, q1, q2
+[0x31,0xff,0x02,0x0d]
+[0x32,0xff,0x44,0x0d]
+
+# CHECK: vabs.f16 d0, d1
+# CHECK: vabs.f16 q0, q1
+[0xb5,0xff,0x01,0x07]
+[0xb5,0xff,0x42,0x07]
+
+# CHECK: vmax.f16 d0, d1, d2
+# CHECK: vmax.f16 q0, q1, q2
+[0x11,0xef,0x02,0x0f]
+[0x12,0xef,0x44,0x0f]
+
+# CHECK: vmin.f16 d0, d1, d2
+# CHECK: vmin.f16 q0, q1, q2
+[0x31,0xef,0x02,0x0f]
+[0x32,0xef,0x44,0x0f]
+
+# CHECK: vmaxnm.f16 d0, d1, d2
+# CHECK: vmaxnm.f16 q0, q1, q2
+[0x11,0xff,0x12,0x0f]
+[0x12,0xff,0x54,0x0f]
+
+# CHECK: vminnm.f16 d0, d1, d2
+# CHECK: vminnm.f16 q0, q1, q2
+[0x31,0xff,0x12,0x0f]
+[0x32,0xff,0x54,0x0f]
+
+# CHECK: vpadd.f16 d0, d1, d2
+[0x11,0xff,0x02,0x0d]
+
+# CHECK: vpmax.f16 d0, d1, d2
+[0x11,0xff,0x02,0x0f]
+
+# CHECK: vpmin.f16 d0, d1, d2
+[0x31,0xff,0x02,0x0f]
+
+# CHECK: vrecpe.f16 d0, d1
+# CHECK: vrecpe.f16 q0, q1
+[0xb7,0xff,0x01,0x05]
+[0xb7,0xff,0x42,0x05]
+
+# CHECK: vrecps.f16 d0, d1, d2
+# CHECK: vrecps.f16 q0, q1, q2
+[0x11,0xef,0x12,0x0f]
+[0x12,0xef,0x54,0x0f]
+
+# CHECK: vrsqrte.f16 d0, d1
+# CHECK: vrsqrte.f16 q0, q1
+[0xb7,0xff,0x81,0x05]
+[0xb7,0xff,0xc2,0x05]
+
+# CHECK: vrsqrts.f16 d0, d1, d2
+# CHECK: vrsqrts.f16 q0, q1, q2
+[0x31,0xef,0x12,0x0f]
+[0x32,0xef,0x54,0x0f]
+
+# CHECK: vneg.f16 d0, d1
+# CHECK: vneg.f16 q0, q1
+[0xb5,0xff,0x81,0x07]
+[0xb5,0xff,0xc2,0x07]
+
+# CHECK: vcvt.s16.f16 d0, d1
+# CHECK: vcvt.u16.f16 d0, d1
+# CHECK: vcvt.f16.s16 d0, d1
+# CHECK: vcvt.f16.u16 d0, d1
+# CHECK: vcvt.s16.f16 q0, q1
+# CHECK: vcvt.u16.f16 q0, q1
+# CHECK: vcvt.f16.s16 q0, q1
+# CHECK: vcvt.f16.u16 q0, q1
+[0xb7,0xff,0x01,0x07]
+[0xb7,0xff,0x81,0x07]
+[0xb7,0xff,0x01,0x06]
+[0xb7,0xff,0x81,0x06]
+[0xb7,0xff,0x42,0x07]
+[0xb7,0xff,0xc2,0x07]
+[0xb7,0xff,0x42,0x06]
+[0xb7,0xff,0xc2,0x06]
+
+# CHECK: vcvta.s16.f16 d0, d1
+# CHECK: vcvta.s16.f16 q0, q1
+# CHECK: vcvta.u16.f16 d0, d1
+# CHECK: vcvta.u16.f16 q0, q1
+[0xb7,0xff,0x01,0x00]
+[0xb7,0xff,0x42,0x00]
+[0xb7,0xff,0x81,0x00]
+[0xb7,0xff,0xc2,0x00]
+
+# CHECK: vcvtm.s16.f16 d0, d1
+# CHECK: vcvtm.s16.f16 q0, q1
+# CHECK: vcvtm.u16.f16 d0, d1
+# CHECK: vcvtm.u16.f16 q0, q1
+[0xb7,0xff,0x01,0x03]
+[0xb7,0xff,0x42,0x03]
+[0xb7,0xff,0x81,0x03]
+[0xb7,0xff,0xc2,0x03]
+
+# CHECK: vcvtn.s16.f16 d0, d1
+# CHECK: vcvtn.s16.f16 q0, q1
+# CHECK: vcvtn.u16.f16 d0, d1
+# CHECK: vcvtn.u16.f16 q0, q1
+[0xb7,0xff,0x01,0x01]
+[0xb7,0xff,0x42,0x01]
+[0xb7,0xff,0x81,0x01]
+[0xb7,0xff,0xc2,0x01]
+
+# CHECK: vcvtp.s16.f16 d0, d1
+# CHECK: vcvtp.s16.f16 q0, q1
+# CHECK: vcvtp.u16.f16 d0, d1
+# CHECK: vcvtp.u16.f16 q0, q1
+[0xb7,0xff,0x01,0x02]
+[0xb7,0xff,0x42,0x02]
+[0xb7,0xff,0x81,0x02]
+[0xb7,0xff,0xc2,0x02]
+
+# CHECK: vcvt.s16.f16 d0, d1, #1
+# CHECK: vcvt.u16.f16 d0, d1, #2
+# CHECK: vcvt.f16.s16 d0, d1, #3
+# CHECK: vcvt.f16.u16 d0, d1, #4
+# CHECK: vcvt.s16.f16 q0, q1, #5
+# CHECK: vcvt.u16.f16 q0, q1, #6
+# CHECK: vcvt.f16.s16 q0, q1, #7
+# CHECK: vcvt.f16.u16 q0, q1, #8
+[0xbf,0xef,0x11,0x0d]
+[0xbe,0xff,0x11,0x0d]
+[0xbd,0xef,0x11,0x0c]
+[0xbc,0xff,0x11,0x0c]
+[0xbb,0xef,0x52,0x0d]
+[0xba,0xff,0x52,0x0d]
+[0xb9,0xef,0x52,0x0c]
+[0xb8,0xff,0x52,0x0c]
+
+# CHECK: vrinta.f16 d0, d1
+# CHECK: vrinta.f16 q0, q1
+[0xb6,0xff,0x01,0x05]
+[0xb6,0xff,0x42,0x05]
+
+# CHECK: vrintm.f16 d0, d1
+# CHECK: vrintm.f16 q0, q1
+[0xb6,0xff,0x81,0x06]
+[0xb6,0xff,0xc2,0x06]
+
+# CHECK: vrintn.f16 d0, d1
+# CHECK: vrintn.f16 q0, q1
+[0xb6,0xff,0x01,0x04]
+[0xb6,0xff,0x42,0x04]
+
+# CHECK: vrintp.f16 d0, d1
+# CHECK: vrintp.f16 q0, q1
+[0xb6,0xff,0x81,0x07]
+[0xb6,0xff,0xc2,0x07]
+
+# CHECK: vrintx.f16 d0, d1
+# CHECK: vrintx.f16 q0, q1
+[0xb6,0xff,0x81,0x04]
+[0xb6,0xff,0xc2,0x04]
+
+# CHECK: vrintz.f16 d0, d1
+# CHECK: vrintz.f16 q0, q1
+[0xb6,0xff,0x81,0x05]
+[0xb6,0xff,0xc2,0x05]
+
+# Existing VMOV(immediate, Advanced SIMD) instructions within the encoding
+# space of the new FP16 VCVT(between floating - point and fixed - point,
+# Advanced SIMD):
+# 1 -- VCVT op
+# 2 -- VCVT FP size
+# 4 -- Q
+# 2 -- VMOV op
+[0xc7,0xef,0x10,0x0c]
+[0xc7,0xef,0x10,0x0d]
+[0xc7,0xef,0x10,0x0e]
+[0xc7,0xef,0x10,0x0f]
+[0xc7,0xef,0x20,0x0c]
+[0xc7,0xef,0x20,0x0d]
+[0xc7,0xef,0x20,0x0e]
+[0xc7,0xef,0x20,0x0f]
+[0xc7,0xef,0x50,0x0c]
+[0xc7,0xef,0x50,0x0d]
+[0xc7,0xef,0x50,0x0e]
+[0xc7,0xef,0x50,0x0f]
+[0xc7,0xef,0x70,0x0c]
+[0xc7,0xef,0x70,0x0d]
+[0xc7,0xef,0x70,0x0e]
+[0xc7,0xef,0x70,0x0f]
+# CHECK: vmov.i32 d16, #0x70ff
+# CHECK: vmov.i32 d16, #0x70ffff
+# CHECK: vmov.i8 d16, #0x70
+# CHECK: vmov.f32 d16, #1.000000e+00
+# CHECK: vmull.s8 q8, d7, d16
+# STDERR: warning: invalid instruction encoding
+# STDERR-NEXT: [0x20,0x0d,0xc7,0xf2]
+# CHECK: vmull.p8 q8, d7, d16
+# STDERR: warning: invalid instruction encoding
+# STDERR-NEXT: [0x20,0x0f,0xc7,0xf2]
+# CHECK: vmov.i32 q8, #0x70ff
+# CHECK: vmov.i32 q8, #0x70ffff
+# CHECK: vmov.i8 q8, #0x70
+# CHECK: vmov.f32 q8, #1.000000e+00
+# CHECK: vmvn.i32 q8, #0x70ff
+# CHECK: vmvn.i32 q8, #0x70ffff
+# CHECK: vmov.i64 q8, #0xffffff0000000
+# STDERR: warning: invalid instruction encoding
+# STDERR-NEXT: [0x70,0x0f,0xc7,0xf2]
projects / oota-llvm.git / blobdiff