[ARM] Add support for MVFR2 which is new in ARMv8

[oota-llvm.git] / test / MC / Disassembler / ARM / arm-tests.txt

diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt
index 0536eebb3171b6d7d681e86c627cb428a31094b4..acc2d9fec609c1afa2578f65aeeba75f998510a3 100644 (file)
--- a/test/MC/Disassembler/ARM/arm-tests.txt
+++ b/test/MC/Disassembler/ARM/arm-tests.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 -mcpu=cortex-a9-mp | FileCheck %s
 
 # CHECK:       addpl   r4, pc, #318767104
 0x4c 0x45 0x8f 0x52
@@ -45,8 +45,17 @@
 # CHECK:       isb
 0x6f 0xf0 0x7f 0xf5
 
-# CHECK:       ldclvc  p5, cr15, [r8], #-0
-0x00 0xf5 0x78 0x7c
+# FIXME: LDC encoding information is incorrect. Re-enable this along with more
+# robust testing for other values when we get it fleshed out and working
+# properly.
+# CHECKx:      ldclvc  p5, cr15, [r8], #-0
+#0x00 0xf5 0x78 0x7c
+
+# CHECK:        ldc     p13, c9, [r2, #0]!
+0x00 0x9d 0xb2 0xed
+
+# CHECK:        ldcl    p1, c9, [r3, #0]!
+0x00 0x91 0xf3 0xed
 
 # CHECK:       ldr     r0, [r2], #15
 0x0f 0x00 0x92 0xe4
@@ -54,14 +63,35 @@
 # CHECK:       ldr     r5, [r7, -r10, lsl #2]
 0x0a 0x51 0x17 0xe7
 
+# CHECK:        ldr     r4, [r5, #0]!
+0x00 0x40 0xb5 0xe5
+
+# CHECK:        ldrb    lr, [r10, #0]!
+0x00 0xe0 0xfa 0xe5
+
+# CHECK:       ldrd    r4, r5, [r0, #0]!
+0xd0 0x40 0xe0 0xe1
+
 # CHECK:       ldrh    r0, [r2], #0
 0xb0 0x00 0xd2 0xe0
 
+# CHECK:       ldrh    r0, [r2]
+0xb0 0x00 0xd2 0xe1
+
+# CHECK:       ldrh    lr, [sp, #0]!
+0xb0 0xe0 0xfd 0xe1
+
 # CHECK:       ldrht   r0, [r2], #15
 0xbf 0x00 0xf2 0xe0
 
+# CHECK:        ldrsb   r1, [lr, #0]!
+0xd0 0x10 0xfe 0xe1
+
 # CHECK:       ldrsbtvs        lr, [r2], -r9
-0xd9 0xe9 0x32 0x60
+0xd9 0xe0 0x32 0x60
+
+# CHECK:        ldrsh   r9, [r1, #0]
+0xf0 0x90 0xf1 0xe1
 
 # CHECK:       lsls    r0, r2, #31
 0x82 0x0f 0xb0 0xe1
@@ -101,6 +131,12 @@
 # CHECK:       rfedb   r0!
 0x00 0x0a 0x30 0xf9
 
+# CHECK:        srsdb sp!, #19
+0x13 0x05 0x6d 0xf9
+
+# CHECK: srsia sp, #9
+0x09 0x05 0xcd 0xf8
+
 # CHECK-NOT:   rsbeq   r0, r2, r0, lsl #0
 # CHECK:       rsbeq   r0, r2, r0
 0x00 0x00 0x62 0x00
@@ -149,10 +185,10 @@
 # CHECK: cpsie if, #10
 0xca 0x00 0x0a 0xf1
 
-# CHECK: msr cpsr_fc, r0
+# CHECK: msr CPSR_fc, r0
 0x00 0xf0 0x29 0xe1
 
-# CHECK:       msrmi   cpsr_c, #4043309056
+# CHECK:       msrmi   CPSR_c, #4043309056
 0xf1 0xf4 0x21 0x43
 
 # CHECK: rsbs r6, r7, r8
@@ -168,7 +204,7 @@
 0x15 0xff 0x2f 0x01
 
 # CHECK:       uqadd16mi       r6, r11, r8
-0x18 0x60 0x6b 0x46
+0x18 0x6F 0x6b 0x46
 
 # CHECK:       str     r0, [sp, #4]
 0x04 0x00 0x8d 0xe5
@@ -189,7 +225,7 @@
 0x20 0x51 0x17 0xe6
 
 # CHECK:       strdeq  r2, r3, [r0], -r8
-0xf8 0x24 0x00 0x00
+0xf8 0x20 0x00 0x00
 
 # CHECK:       ldrdeq  r2, r3, [r0], -r12
 0xdc 0x24 0x00 0x00
@@ -203,7 +239,7 @@
 # CHECK:       vldmdb  r2!, {s7, s8, s9, s10, s11}
 0x05 0x3a 0x72 0xed
 
-# CHECK:       vldr.32 s23, [r2, #660]
+# CHECK:       vldr    s23, [r2, #660]
 0xa5 0xba 0xd2 0xed
 
 # CHECK:       strtvc  r5, [r3], r0, lsr #20
@@ -221,7 +257,7 @@
 # CHECK:       umull   r1, r2, r3, r4
 0x93 0x14 0x82 0xe0
 
-# CHECK:       pld     [pc, #-0]
+# CHECK:       pldw    [pc, #-0]
 0x00 0xf0 0x1f 0xf5
 
 # CHECK:       pli     [pc, #-0]
@@ -230,12 +266,33 @@
 # CHECK:       pli     [r3, r1, lsl #2]
 0x01 0xf1 0xd3 0xf6
 
-# CHECK:       stc     p2, cr4, [r9], {157}
+# CHECK:       stc     p2, c4, [r9], {157}
 0x9d 0x42 0x89 0xec
 
-# CHECK:       stc2    p2, cr4, [r9], {157}
+# CHECK:        stc     p15, c0, [r3, #0]!
+0x00 0x0f 0xa3 0xed
+
+# CHECK:       stc2    p2, c4, [r9], {157}
 0x9d 0x42 0x89 0xfc
 
+# CHECK:       stcl    p13, c12, [r9, #0]!
+0x00 0xcd 0xe9 0xed
+
+# CHECK:        str     pc, [r11, #0]!
+0x00 0xf0 0xab 0xe5
+
+# CHECK:        strb    r9, [r10, #0]!
+0x00 0x90 0xea 0xe5
+
+# CHECK:        strd    r12, sp, [r6, #0]!
+0xf0 0xc0 0xe6 0xe1
+
+# CHECK:        strh    r7, [r9, #0]!
+0xb0 0x70 0xe9 0xe1
+
+# CHECK:       bne #-24
+0xfa 0xff 0xff 0x1a
+
 # CHECK:       blx     #60
 0x0f 0x00 0x00 0xfa
 
@@ -287,3 +344,21 @@
 
 # CHECK:       nop
 0x00 0xf0 0x20 0xe3
+
+# CHECK:        andeq   r0, r0, r0, lsr #32
+0x20 0x00 0x00 0x00
+
+# CHECK: strb  r3, [r2], #1
+0x01 0x30 0xc2 0xe4
+
+# CHECK:         strheq  r0, [r0, -r0]
+0xb0 0x00 0x00 0x01
+
+# CHECK: rfedb #4!
+0x14 0x0 0x32 0xf9
+
+# CHECK: stc2l p0, c0, [r2], #-96
+0x18 0x0 0x62 0xfc
+
+# CHECK: ldmgt sp!, {r9}
+0x00 0x02 0xbd 0xc8