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Make it clear in which sections these relocations are.
[oota-llvm.git] / test / MC / ARM / neon-bitwise-encoding.s
diff --git a/test/MC/ARM/neon-bitwise-encoding.s b/test/MC/ARM/neon-bitwise-encoding.s
index 1b4ca33592ecbe5ae516001f7219c8fdd00e2f6c..d142dbabec9e9521b3f3a5647fa9056d79fdda29 100644 (file)
--- a/test/MC/ARM/neon-bitwise-encoding.s
+++ b/test/MC/ARM/neon-bitwise-encoding.s
@@ -1,4 +1,5 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s \
+@ RUN: | FileCheck %s
 
        vand    d16, d17, d16
        vand    q8, q8, q9
@@ -28,13 +29,63 @@
 
        vbic    d16, d17, d16
        vbic    q8, q8, q9
+       vbic q10, q11
+       vbic d9, d1
+       vbic.i16        d16, #0xFF00
+       vbic.i16        q8,  #0xFF00
+       vbic.i16        d16, #0x00FF
+       vbic.i16        q8,  #0x00FF
        vbic.i32        d16, #0xFF000000
-       vbic.i32        q8, #0xFF000000
+       vbic.i32        q8,  #0xFF000000
+       vbic.i32        d16, #0x00FF0000
+       vbic.i32        q8,  #0x00FF0000
+       vbic.i32        d16, #0x0000FF00
+       vbic.i32        q8,  #0x0000FF00
+       vbic.i32        d16, #0x000000FF
+       vbic.i32        q8,  #0x000000FF
 
 @ CHECK: vbic  d16, d17, d16           @ encoding: [0xb0,0x01,0x51,0xf2]
 @ CHECK: vbic  q8, q8, q9              @ encoding: [0xf2,0x01,0x50,0xf2]
+@ CHECK: vbic  q10, q10, q11           @ encoding: [0xf6,0x41,0x54,0xf2]
+@ CHECK: vbic  d9, d9, d1              @ encoding: [0x11,0x91,0x19,0xf2]
+@ CHECK: vbic.i16      d16, #0xff00    @ encoding: [0x3f,0x0b,0xc7,0xf3]
+@ CHECK: vbic.i16      q8, #0xff00     @ encoding: [0x7f,0x0b,0xc7,0xf3]
+@ CHECK: vbic.i16      d16, #0xff      @ encoding: [0x3f,0x09,0xc7,0xf3]
+@ CHECK: vbic.i16      q8, #0xff       @ encoding: [0x7f,0x09,0xc7,0xf3]
 @ CHECK: vbic.i32      d16, #0xff000000 @ encoding: [0x3f,0x07,0xc7,0xf3]
 @ CHECK: vbic.i32      q8, #0xff000000 @ encoding: [0x7f,0x07,0xc7,0xf3]
+@ CHECK: vbic.i32      d16, #0xff0000  @ encoding: [0x3f,0x05,0xc7,0xf3]
+@ CHECK: vbic.i32      q8, #0xff0000   @ encoding: [0x7f,0x05,0xc7,0xf3]
+@ CHECK: vbic.i32      d16, #0xff00    @ encoding: [0x3f,0x03,0xc7,0xf3]
+@ CHECK: vbic.i32      q8, #0xff00     @ encoding: [0x7f,0x03,0xc7,0xf3]
+@ CHECK: vbic.i32      d16, #0xff      @ encoding: [0x3f,0x01,0xc7,0xf3]
+@ CHECK: vbic.i32      q8, #0xff       @ encoding: [0x7f,0x01,0xc7,0xf3]
+
+       vand.i16 d10, #0xff03
+       vand.i16 q10, #0xff03
+       vand.i16 d10, #0x03ff
+       vand.i16 q10, #0x03ff
+       vand.i32 d10, #0x03ffffff
+       vand.i32 q10, #0x03ffffff
+       vand.i32 d10, #0xff03ffff
+       vand.i32 q10, #0xff03ffff
+       vand.i32 d10, #0xffff03ff
+       vand.i32 q10, #0xffff03ff
+       vand.i32 d10, #0xffffff03
+       vand.i32 q10, #0xffffff03
+
+@ CHECK: vbic.i16      d10, #0xfc      @ encoding: [0x3c,0xa9,0x87,0xf3]
+@ CHECK: vbic.i16      q10, #0xfc      @ encoding: [0x7c,0x49,0xc7,0xf3]
+@ CHECK: vbic.i16      d10, #0xfc00    @ encoding: [0x3c,0xab,0x87,0xf3]
+@ CHECK: vbic.i16      q10, #0xfc00    @ encoding: [0x7c,0x4b,0xc7,0xf3]
+@ CHECK: vbic.i32      d10, #0xfc000000 @ encoding: [0x3c,0xa7,0x87,0xf3]
+@ CHECK: vbic.i32      q10, #0xfc000000 @ encoding: [0x7c,0x47,0xc7,0xf3]
+@ CHECK: vbic.i32      d10, #0xfc0000  @ encoding: [0x3c,0xa5,0x87,0xf3]
+@ CHECK: vbic.i32      q10, #0xfc0000  @ encoding: [0x7c,0x45,0xc7,0xf3]
+@ CHECK: vbic.i32      d10, #0xfc00    @ encoding: [0x3c,0xa3,0x87,0xf3]
+@ CHECK: vbic.i32      q10, #0xfc00    @ encoding: [0x7c,0x43,0xc7,0xf3]
+@ CHECK: vbic.i32      d10, #0xfc      @ encoding: [0x3c,0xa1,0x87,0xf3]
+@ CHECK: vbic.i32      q10, #0xfc      @ encoding: [0x7c,0x41,0xc7,0xf3]
 
        vorn    d16, d17, d16
        vorn    q8, q8, q9
@@ -250,6 +301,42 @@
        veor.f   q8, q2
        veor.i64 q8, q2
 
+       vclt.s16 q5, #0
+       vclt.s16 d5, #0
+
+       vceq.s16 q5, q3
+       vceq.s16 d5, d3
+
+       vcgt.s16 q5, q3
+       vcgt.s16 d5, d3
+
+       vcge.s16 q5, q3
+       vcge.s16 d5, d3
+
+       vcgt.s16 q5, #0
+       vcgt.s16 d5, #0
+
+       vcge.s16 q5, #0
+       vcge.s16 d5, #0
+
+       vceq.s16 q5, #0
+       vceq.s16 d5, #0
+
+       vcle.s16 q5, #0
+       vcle.s16 d5, #0
+
+       vacge.f32 d5, d30
+       vacge.f32 q5, q3
+
+       vacgt.f32 d5, d30
+       vacgt.f32 q5, q3
+
+@ FIXME: We don't have an alias that reverses the operands
+@  vacle.f32 d5, d30 
+@  vacle.f32 q5, q3 
+@  vaclt.f32 d5, d30
+@  vaclt.f32 q5, q3
+
 @ CHECK: vand  q6, q6, q5              @ encoding: [0x5a,0xc1,0x0c,0xf2]
 @ CHECK: vand  q6, q6, q5              @ encoding: [0x5a,0xc1,0x0c,0xf2]
 @ CHECK: vand  q7, q7, q1              @ encoding: [0x52,0xe1,0x0e,0xf2]
@@ -267,3 +354,32 @@
 @ CHECK: veor  q7, q7, q1              @ encoding: [0x52,0xe1,0x0e,0xf3]
 @ CHECK: veor  q8, q8, q2              @ encoding: [0xd4,0x01,0x40,0xf3]
 @ CHECK: veor  q8, q8, q2              @ encoding: [0xd4,0x01,0x40,0xf3]
+@ CHECK: vclt.s16        q5, q5, #0      @ encoding: [0x4a,0xa2,0xb5,0xf3]
+@ CHECK: vclt.s16        d5, d5, #0      @ encoding: [0x05,0x52,0xb5,0xf3]
+
+@ CHECK: vceq.i16        q5, q5, q3      @ encoding: [0x56,0xa8,0x1a,0xf3]
+@ CHECK: vceq.i16        d5, d5, d3      @ encoding: [0x13,0x58,0x15,0xf3]
+
+@ CHECK: vcgt.s16        q5, q5, q3      @ encoding: [0x46,0xa3,0x1a,0xf2]
+@ CHECK: vcgt.s16        d5, d5, d3      @ encoding: [0x03,0x53,0x15,0xf2]
+
+@ CHECK: vcge.s16        q5, q5, q3      @ encoding: [0x56,0xa3,0x1a,0xf2]
+@ CHECK: vcge.s16        d5, d5, d3      @ encoding: [0x13,0x53,0x15,0xf2]
+
+@ CHECK: vcgt.s16        q5, q5, #0      @ encoding: [0x4a,0xa0,0xb5,0xf3]
+@ CHECK: vcgt.s16        d5, d5, #0      @ encoding: [0x05,0x50,0xb5,0xf3]
+
+@ CHECK: vcge.s16        q5, q5, #0      @ encoding: [0xca,0xa0,0xb5,0xf3]
+@ CHECK: vcge.s16        d5, d5, #0      @ encoding: [0x85,0x50,0xb5,0xf3]
+
+@ CHECK: vceq.i16        q5, q5, #0      @ encoding: [0x4a,0xa1,0xb5,0xf3]
+@ CHECK: vceq.i16        d5, d5, #0      @ encoding: [0x05,0x51,0xb5,0xf3]
+
+@ CHECK: vcle.s16        q5, q5, #0      @ encoding: [0xca,0xa1,0xb5,0xf3]
+@ CHECK: vcle.s16        d5, d5, #0      @ encoding: [0x85,0x51,0xb5,0xf3]
+
+@ CHECK: vacge.f32       d5, d5, d30     @ encoding: [0x3e,0x5e,0x05,0xf3]
+@ CHECK: vacge.f32       q5, q5, q3      @ encoding: [0x56,0xae,0x0a,0xf3]
+
+@ CHECK: vacgt.f32       d5, d5, d30     @ encoding: [0x3e,0x5e,0x25,0xf3]
+@ CHECK: vacgt.f32       q5, q5, q3      @ encoding: [0x56,0xae,0x2a,0xf3]
C/C++ LLVM-based compilers that forbids OOTA behaviors