Fix tests not to depend on specific regalloc or instruction order.

[oota-llvm.git] / test / CodeGen / X86 / x86-64-tls-1.ll

diff --git a/test/CodeGen/X86/x86-64-tls-1.ll b/test/CodeGen/X86/x86-64-tls-1.ll
index b172e9d51b943b6b4b469ff39d2ed54d00a6e5eb..641786f5a9149d4e276d20bf877a6dd55fe673f3 100644 (file)
--- a/test/CodeGen/X86/x86-64-tls-1.ll
+++ b/test/CodeGen/X86/x86-64-tls-1.ll
@@ -3,8 +3,8 @@
 define i64 @z() nounwind {
 ; FIXME: The codegen here is primitive at best and could be much better.
 ; The add and the moves can be folded together.
-; CHECK: movq    $tm_nest_level@TPOFF, %rcx
-; CHECK: movq    %fs:0, %rax
+; CHECK-DAG: movq    $tm_nest_level@TPOFF, %rcx
+; CHECK-DAG: movq    %fs:0, %rax
 ; CHECK: addl    %ecx, %eax
   ret i64 and (i64 ptrtoint (i32* @tm_nest_level to i64), i64 100)
 }