[X86][SSE] Vectorized i8 and i16 shift operators

[oota-llvm.git] / test / CodeGen / X86 / x86-64-and-mask.ll

diff --git a/test/CodeGen/X86/x86-64-and-mask.ll b/test/CodeGen/X86/x86-64-and-mask.ll
index 07ccb2337e752a2f615b1fed2992eb06dce895a2..c8a832a6d3a2433396b1f1cabb69b5d4baccaf83 100644 (file)
--- a/test/CodeGen/X86/x86-64-and-mask.ll
+++ b/test/CodeGen/X86/x86-64-and-mask.ll
@@ -4,7 +4,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 target triple = "x86_64-apple-darwin8"
 
 ; This should be a single mov, not a load of immediate + andq.
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: movl %edi, %eax
 
 define i64 @test(i64 %x) nounwind {
@@ -14,7 +14,7 @@ entry:
 }
 
 ; This copy can't be coalesced away because it needs the implicit zero-extend.
-; CHECK: bbb:
+; CHECK-LABEL: bbb:
 ; CHECK: movl %edi, %edi
 
 define void @bbb(i64 %x) nounwind {
@@ -26,7 +26,7 @@ define void @bbb(i64 %x) nounwind {
 ; This should use a 32-bit and with implicit zero-extension, not a 64-bit and
 ; with a separate mov to materialize the mask.
 ; rdar://7527390
-; CHECK: ccc:
+; CHECK-LABEL: ccc:
 ; CHECK: andl $-1048593, %edi
 
 declare void @foo(i64 %x) nounwind
@@ -38,9 +38,9 @@ define void @ccc(i64 %x) nounwind {
 }
 
 ; This requires a mov and a 64-bit and.
-; CHECK: ddd:
+; CHECK-LABEL: ddd:
 ; CHECK: movabsq $4294967296, %r
-; CHECK: andq %rax, %rdi
+; CHECK: andq %r{{..}}, %r{{..}}
 
 define void @ddd(i64 %x) nounwind {
   %t = and i64 %x, 4294967296