Handle vector move / load which zero the destination register top bits (i.e. movd...

[oota-llvm.git] / test / CodeGen / X86 / vec_set-D.ll

diff --git a/test/CodeGen/X86/vec_set-D.ll b/test/CodeGen/X86/vec_set-D.ll
new file mode 100644 (file)
index 0000000..71bdd84
--- /dev/null
+++ b/test/CodeGen/X86/vec_set-D.ll
@@ -0,0 +1,7 @@
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movq
+
+define <4 x i32> @t(i32 %x, i32 %y) nounwind  {
+       %tmp1 = insertelement <4 x i32> zeroinitializer, i32 %x, i32 0
+       %tmp2 = insertelement <4 x i32> %tmp1, i32 %y, i32 1
+       ret <4 x i32> %tmp2
+}