;
; SSE41-LABEL: max_gt_v4i32c:
; SSE41: # BB#0:
-; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
-; SSE41-NEXT: pmaxud {{.*}}(%rip), %xmm0
+; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
; SSE41-NEXT: retq
;
; SSE42-LABEL: max_gt_v4i32c:
; SSE42: # BB#0:
-; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
-; SSE42-NEXT: pmaxud {{.*}}(%rip), %xmm0
+; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
; SSE42-NEXT: retq
;
; AVX-LABEL: max_gt_v4i32c:
; AVX: # BB#0:
-; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
-; AVX-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
; AVX-NEXT: retq
%1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
- %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 1, i32 0
+ %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
%3 = icmp ugt <4 x i32> %1, %2
%4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
ret <4 x i32> %4
;
; SSE41-LABEL: max_gt_v8i32c:
; SSE41: # BB#0:
-; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
-; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
-; SSE41-NEXT: pmaxud {{.*}}(%rip), %xmm0
-; SSE41-NEXT: pmaxud {{.*}}(%rip), %xmm1
+; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
+; SSE41-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
; SSE41-NEXT: retq
;
; SSE42-LABEL: max_gt_v8i32c:
; SSE42: # BB#0:
-; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
-; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
-; SSE42-NEXT: pmaxud {{.*}}(%rip), %xmm0
-; SSE42-NEXT: pmaxud {{.*}}(%rip), %xmm1
+; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
+; SSE42-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
; SSE42-NEXT: retq
;
-; AVX1-LABEL: max_gt_v8i32c:
-; AVX1: # BB#0:
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
-; AVX1-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,3,5,7]
-; AVX1-NEXT: vpmaxud {{.*}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: max_gt_v8i32c:
-; AVX2: # BB#0:
-; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
-; AVX2-NEXT: vpmaxud {{.*}}(%rip), %ymm0, %ymm0
-; AVX2-NEXT: retq
-;
-; AVX512-LABEL: max_gt_v8i32c:
-; AVX512: # BB#0:
-; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
-; AVX512-NEXT: vpmaxud {{.*}}(%rip), %ymm0, %ymm0
-; AVX512-NEXT: retq
+; AVX-LABEL: max_gt_v8i32c:
+; AVX: # BB#0:
+; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
+; AVX-NEXT: retq
%1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
- %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 1, i32 0
+ %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
%3 = icmp ugt <8 x i32> %1, %2
%4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
ret <8 x i32> %4
;
; SSE41-LABEL: max_gt_v8i16c:
; SSE41: # BB#0:
-; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
-; SSE41-NEXT: pmaxuw {{.*}}(%rip), %xmm0
+; SSE41-NEXT: movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
; SSE41-NEXT: retq
;
; SSE42-LABEL: max_gt_v8i16c:
; SSE42: # BB#0:
-; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
-; SSE42-NEXT: pmaxuw {{.*}}(%rip), %xmm0
+; SSE42-NEXT: movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
; SSE42-NEXT: retq
;
; AVX-LABEL: max_gt_v8i16c:
; AVX: # BB#0:
-; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
-; AVX-NEXT: vpmaxuw {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
; AVX-NEXT: retq
- %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i16 0
- %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 1, i16 0
+ %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
+ %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
%3 = icmp ugt <8 x i16> %1, %2
%4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
ret <8 x i16> %4
;
; SSE41-LABEL: max_gt_v16i16c:
; SSE41: # BB#0:
-; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
-; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
-; SSE41-NEXT: pmaxuw {{.*}}(%rip), %xmm0
-; SSE41-NEXT: pmaxuw {{.*}}(%rip), %xmm1
+; SSE41-NEXT: movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0]
+; SSE41-NEXT: movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8]
; SSE41-NEXT: retq
;
; SSE42-LABEL: max_gt_v16i16c:
; SSE42: # BB#0:
-; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
-; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
-; SSE42-NEXT: pmaxuw {{.*}}(%rip), %xmm0
-; SSE42-NEXT: pmaxuw {{.*}}(%rip), %xmm1
+; SSE42-NEXT: movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0]
+; SSE42-NEXT: movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8]
; SSE42-NEXT: retq
;
-; AVX1-LABEL: max_gt_v16i16c:
-; AVX1: # BB#0:
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
-; AVX1-NEXT: vpmaxuw {{.*}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
-; AVX1-NEXT: vpmaxuw {{.*}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: max_gt_v16i16c:
-; AVX2: # BB#0:
-; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
-; AVX2-NEXT: vpmaxuw {{.*}}(%rip), %ymm0, %ymm0
-; AVX2-NEXT: retq
-;
-; AVX512-LABEL: max_gt_v16i16c:
-; AVX512: # BB#0:
-; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
-; AVX512-NEXT: vpmaxuw {{.*}}(%rip), %ymm0, %ymm0
-; AVX512-NEXT: retq
- %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i16 0
- %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 1, i16 0
+; AVX-LABEL: max_gt_v16i16c:
+; AVX: # BB#0:
+; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65535,65534,65533,65532,65533,65534,65535,0,7,6,5,4,5,6,7,8]
+; AVX-NEXT: retq
+ %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
+ %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
%3 = icmp ugt <16 x i16> %1, %2
%4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
ret <16 x i16> %4
define <16 x i8> @max_gt_v16i8c() {
; SSE-LABEL: max_gt_v16i8c:
; SSE: # BB#0:
-; SSE-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
-; SSE-NEXT: pmaxub {{.*}}(%rip), %xmm0
+; SSE-NEXT: movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
; SSE-NEXT: retq
;
; AVX-LABEL: max_gt_v16i8c:
; AVX: # BB#0:
-; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
-; AVX-NEXT: vpmaxub {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
; AVX-NEXT: retq
- %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i8 0
- %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 1, i8 0
+ %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
+ %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
%3 = icmp ugt <16 x i8> %1, %2
%4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
ret <16 x i8> %4
define <4 x i32> @max_ge_v4i32c() {
; SSE2-LABEL: max_ge_v4i32c:
; SSE2: # BB#0:
-; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [2147483649,2147483641,2147483655,2147483649]
+; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [2147483647,2147483641,2147483655,2147483649]
; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
; SSE2-NEXT: pcmpeqd %xmm1, %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm1
;
; SSE41-LABEL: max_ge_v4i32c:
; SSE41: # BB#0:
-; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
-; SSE41-NEXT: pmaxud {{.*}}(%rip), %xmm0
+; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
; SSE41-NEXT: retq
;
; SSE42-LABEL: max_ge_v4i32c:
; SSE42: # BB#0:
-; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
-; SSE42-NEXT: pmaxud {{.*}}(%rip), %xmm0
+; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
; SSE42-NEXT: retq
;
; AVX-LABEL: max_ge_v4i32c:
; AVX: # BB#0:
-; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
-; AVX-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
; AVX-NEXT: retq
%1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
- %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 1, i32 0
+ %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
%3 = icmp uge <4 x i32> %1, %2
%4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
ret <4 x i32> %4
; SSE2-NEXT: pcmpeqd %xmm2, %xmm2
; SSE2-NEXT: movdqa %xmm1, %xmm3
; SSE2-NEXT: pxor %xmm2, %xmm3
-; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [2147483649,2147483645,2147483643,2147483641]
+; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [2147483647,2147483645,2147483643,2147483641]
; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm2
; SSE2-NEXT: pandn {{.*}}(%rip), %xmm2
;
; SSE41-LABEL: max_ge_v8i32c:
; SSE41: # BB#0:
-; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
-; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
-; SSE41-NEXT: pmaxud {{.*}}(%rip), %xmm0
-; SSE41-NEXT: pmaxud {{.*}}(%rip), %xmm1
+; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
+; SSE41-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
; SSE41-NEXT: retq
;
; SSE42-LABEL: max_ge_v8i32c:
; SSE42: # BB#0:
-; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
-; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
-; SSE42-NEXT: pmaxud {{.*}}(%rip), %xmm0
-; SSE42-NEXT: pmaxud {{.*}}(%rip), %xmm1
+; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
+; SSE42-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
; SSE42-NEXT: retq
;
-; AVX1-LABEL: max_ge_v8i32c:
-; AVX1: # BB#0:
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
-; AVX1-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,3,5,7]
-; AVX1-NEXT: vpmaxud {{.*}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: max_ge_v8i32c:
-; AVX2: # BB#0:
-; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
-; AVX2-NEXT: vpmaxud {{.*}}(%rip), %ymm0, %ymm0
-; AVX2-NEXT: retq
-;
-; AVX512-LABEL: max_ge_v8i32c:
-; AVX512: # BB#0:
-; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
-; AVX512-NEXT: vpmaxud {{.*}}(%rip), %ymm0, %ymm0
-; AVX512-NEXT: retq
+; AVX-LABEL: max_ge_v8i32c:
+; AVX: # BB#0:
+; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
+; AVX-NEXT: retq
%1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
- %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 1, i32 0
+ %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
%3 = icmp uge <8 x i32> %1, %2
%4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
ret <8 x i32> %4
; SSE2-LABEL: max_ge_v8i16c:
; SSE2: # BB#0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65529,65531,65533,65535,1,3,5,7]
-; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [1,65533,65531,65529,7,5,3,1]
+; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [65535,65533,65531,65529,7,5,3,1]
; SSE2-NEXT: movdqa %xmm2, %xmm3
; SSE2-NEXT: psubusw %xmm1, %xmm3
; SSE2-NEXT: pxor %xmm0, %xmm0
;
; SSE41-LABEL: max_ge_v8i16c:
; SSE41: # BB#0:
-; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
-; SSE41-NEXT: pmaxuw {{.*}}(%rip), %xmm0
+; SSE41-NEXT: movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
; SSE41-NEXT: retq
;
; SSE42-LABEL: max_ge_v8i16c:
; SSE42: # BB#0:
-; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
-; SSE42-NEXT: pmaxuw {{.*}}(%rip), %xmm0
+; SSE42-NEXT: movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
; SSE42-NEXT: retq
;
; AVX-LABEL: max_ge_v8i16c:
; AVX: # BB#0:
-; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
-; AVX-NEXT: vpmaxuw {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
; AVX-NEXT: retq
- %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i16 0
- %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 1, i16 0
+ %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
+ %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
%3 = icmp uge <8 x i16> %1, %2
%4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
ret <8 x i16> %4
; SSE2: # BB#0:
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [65529,65530,65531,65532,65533,65534,65535,0]
; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [1,2,3,4,5,6,7,8]
-; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [1,65534,65533,65532,65531,65530,65529,0]
+; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [65535,65534,65533,65532,65531,65530,65529,0]
; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [7,6,5,4,3,2,1,0]
; SSE2-NEXT: movdqa %xmm5, %xmm1
; SSE2-NEXT: psubusw %xmm3, %xmm1
;
; SSE41-LABEL: max_ge_v16i16c:
; SSE41: # BB#0:
-; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
-; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
-; SSE41-NEXT: pmaxuw {{.*}}(%rip), %xmm0
-; SSE41-NEXT: pmaxuw {{.*}}(%rip), %xmm1
+; SSE41-NEXT: movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0]
+; SSE41-NEXT: movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8]
; SSE41-NEXT: retq
;
; SSE42-LABEL: max_ge_v16i16c:
; SSE42: # BB#0:
-; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
-; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
-; SSE42-NEXT: pmaxuw {{.*}}(%rip), %xmm0
-; SSE42-NEXT: pmaxuw {{.*}}(%rip), %xmm1
+; SSE42-NEXT: movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0]
+; SSE42-NEXT: movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8]
; SSE42-NEXT: retq
;
-; AVX1-LABEL: max_ge_v16i16c:
-; AVX1: # BB#0:
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
-; AVX1-NEXT: vpmaxuw {{.*}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
-; AVX1-NEXT: vpmaxuw {{.*}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: max_ge_v16i16c:
-; AVX2: # BB#0:
-; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
-; AVX2-NEXT: vpmaxuw {{.*}}(%rip), %ymm0, %ymm0
-; AVX2-NEXT: retq
-;
-; AVX512-LABEL: max_ge_v16i16c:
-; AVX512: # BB#0:
-; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
-; AVX512-NEXT: vpmaxuw {{.*}}(%rip), %ymm0, %ymm0
-; AVX512-NEXT: retq
- %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i16 0
- %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 1, i16 0
+; AVX-LABEL: max_ge_v16i16c:
+; AVX: # BB#0:
+; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65535,65534,65533,65532,65533,65534,65535,0,7,6,5,4,5,6,7,8]
+; AVX-NEXT: retq
+ %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
+ %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
%3 = icmp uge <16 x i16> %1, %2
%4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
ret <16 x i16> %4
define <16 x i8> @max_ge_v16i8c() {
; SSE-LABEL: max_ge_v16i8c:
; SSE: # BB#0:
-; SSE-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
-; SSE-NEXT: pmaxub {{.*}}(%rip), %xmm0
+; SSE-NEXT: movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
; SSE-NEXT: retq
;
; AVX-LABEL: max_ge_v16i8c:
; AVX: # BB#0:
-; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
-; AVX-NEXT: vpmaxub {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
; AVX-NEXT: retq
- %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i8 0
- %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 1, i8 0
+ %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
+ %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
%3 = icmp uge <16 x i8> %1, %2
%4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
ret <16 x i8> %4
}
-define <2 x i64> @max_lt_v2i64c() {
-; SSE2-LABEL: max_lt_v2i64c:
+define <2 x i64> @min_lt_v2i64c() {
+; SSE2-LABEL: min_lt_v2i64c:
; SSE2: # BB#0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [18446744073709551609,7]
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [18446744073709551615,1]
; SSE2-NEXT: por %xmm3, %xmm0
; SSE2-NEXT: retq
;
-; SSE41-LABEL: max_lt_v2i64c:
+; SSE41-LABEL: min_lt_v2i64c:
; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [18446744073709551609,7]
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [18446744073709551615,1]
; SSE41-NEXT: movapd %xmm1, %xmm0
; SSE41-NEXT: retq
;
-; SSE42-LABEL: max_lt_v2i64c:
+; SSE42-LABEL: min_lt_v2i64c:
; SSE42: # BB#0:
; SSE42-NEXT: movapd {{.*#+}} xmm1 = [18446744073709551615,1]
; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [9223372036854775807,9223372036854775809]
; SSE42-NEXT: movapd %xmm1, %xmm0
; SSE42-NEXT: retq
;
-; AVX-LABEL: max_lt_v2i64c:
+; AVX-LABEL: min_lt_v2i64c:
; AVX: # BB#0:
; AVX-NEXT: vmovapd {{.*#+}} xmm0 = [18446744073709551615,1]
; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775807,9223372036854775809]
ret <2 x i64> %4
}
-define <4 x i64> @max_lt_v4i64c() {
-; SSE2-LABEL: max_lt_v4i64c:
+define <4 x i64> @min_lt_v4i64c() {
+; SSE2-LABEL: min_lt_v4i64c:
; SSE2: # BB#0:
; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [18446744073709551609,18446744073709551615]
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [1,7]
; SSE2-NEXT: por %xmm2, %xmm1
; SSE2-NEXT: retq
;
-; SSE41-LABEL: max_lt_v4i64c:
+; SSE41-LABEL: min_lt_v4i64c:
; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm5 = [18446744073709551609,18446744073709551615]
; SSE41-NEXT: movdqa {{.*#+}} xmm8 = [1,7]
; SSE41-NEXT: movapd %xmm2, %xmm0
; SSE41-NEXT: retq
;
-; SSE42-LABEL: max_lt_v4i64c:
+; SSE42-LABEL: min_lt_v4i64c:
; SSE42: # BB#0:
; SSE42-NEXT: movapd {{.*#+}} xmm1 = [7,1]
; SSE42-NEXT: movapd {{.*#+}} xmm2 = [18446744073709551615,18446744073709551609]
; SSE42-NEXT: movapd %xmm2, %xmm0
; SSE42-NEXT: retq
;
-; AVX1-LABEL: max_lt_v4i64c:
+; AVX1-LABEL: min_lt_v4i64c:
; AVX1: # BB#0:
; AVX1-NEXT: vmovapd {{.*#+}} ymm0 = [18446744073709551615,18446744073709551609,7,1]
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775807,9223372036854775801]
; AVX1-NEXT: vblendvpd %ymm1, {{.*}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq
;
-; AVX2-LABEL: max_lt_v4i64c:
+; AVX2-LABEL: min_lt_v4i64c:
; AVX2: # BB#0:
; AVX2-NEXT: vmovapd {{.*#+}} ymm0 = [18446744073709551615,18446744073709551609,7,1]
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [9223372036854775807,9223372036854775801,9223372036854775815,9223372036854775809]
; AVX2-NEXT: vblendvpd %ymm1, {{.*}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
-; AVX512-LABEL: max_lt_v4i64c:
+; AVX512-LABEL: min_lt_v4i64c:
; AVX512: # BB#0:
; AVX512-NEXT: vmovapd {{.*#+}} ymm0 = [18446744073709551615,18446744073709551609,7,1]
; AVX512-NEXT: vmovdqa {{.*#+}} ymm1 = [9223372036854775807,9223372036854775801,9223372036854775815,9223372036854775809]
ret <4 x i64> %4
}
-define <4 x i32> @max_lt_v4i32c() {
-; SSE2-LABEL: max_lt_v4i32c:
+define <4 x i32> @min_lt_v4i32c() {
+; SSE2-LABEL: min_lt_v4i32c:
; SSE2: # BB#0:
-; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [2147483649,2147483641,2147483655,2147483649]
+; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [2147483647,2147483641,2147483655,2147483649]
; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: pandn {{.*}}(%rip), %xmm1
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: retq
;
-; SSE41-LABEL: max_lt_v4i32c:
+; SSE41-LABEL: min_lt_v4i32c:
; SSE41: # BB#0:
-; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
-; SSE41-NEXT: pminud {{.*}}(%rip), %xmm0
+; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
; SSE41-NEXT: retq
;
-; SSE42-LABEL: max_lt_v4i32c:
+; SSE42-LABEL: min_lt_v4i32c:
; SSE42: # BB#0:
-; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
-; SSE42-NEXT: pminud {{.*}}(%rip), %xmm0
+; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
; SSE42-NEXT: retq
;
-; AVX-LABEL: max_lt_v4i32c:
+; AVX-LABEL: min_lt_v4i32c:
; AVX: # BB#0:
-; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
-; AVX-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
; AVX-NEXT: retq
%1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
- %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 1, i32 0
+ %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
%3 = icmp ult <4 x i32> %1, %2
%4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
ret <4 x i32> %4
}
-define <8 x i32> @max_lt_v8i32c() {
-; SSE2-LABEL: max_lt_v8i32c:
+define <8 x i32> @min_lt_v8i32c() {
+; SSE2-LABEL: min_lt_v8i32c:
; SSE2: # BB#0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483655,2147483653,2147483651,2147483649]
; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
-; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [2147483649,2147483645,2147483643,2147483641]
+; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [2147483647,2147483645,2147483643,2147483641]
; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pandn {{.*}}(%rip), %xmm2
; SSE2-NEXT: por %xmm2, %xmm1
; SSE2-NEXT: retq
;
-; SSE41-LABEL: max_lt_v8i32c:
+; SSE41-LABEL: min_lt_v8i32c:
; SSE41: # BB#0:
-; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
-; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
-; SSE41-NEXT: pminud {{.*}}(%rip), %xmm0
-; SSE41-NEXT: pminud {{.*}}(%rip), %xmm1
+; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
+; SSE41-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
; SSE41-NEXT: retq
;
-; SSE42-LABEL: max_lt_v8i32c:
+; SSE42-LABEL: min_lt_v8i32c:
; SSE42: # BB#0:
-; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
-; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
-; SSE42-NEXT: pminud {{.*}}(%rip), %xmm0
-; SSE42-NEXT: pminud {{.*}}(%rip), %xmm1
+; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
+; SSE42-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
; SSE42-NEXT: retq
;
-; AVX1-LABEL: max_lt_v8i32c:
-; AVX1: # BB#0:
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
-; AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,3,5,7]
-; AVX1-NEXT: vpminud {{.*}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: max_lt_v8i32c:
-; AVX2: # BB#0:
-; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
-; AVX2-NEXT: vpminud {{.*}}(%rip), %ymm0, %ymm0
-; AVX2-NEXT: retq
-;
-; AVX512-LABEL: max_lt_v8i32c:
-; AVX512: # BB#0:
-; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
-; AVX512-NEXT: vpminud {{.*}}(%rip), %ymm0, %ymm0
-; AVX512-NEXT: retq
+; AVX-LABEL: min_lt_v8i32c:
+; AVX: # BB#0:
+; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
+; AVX-NEXT: retq
%1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
- %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 1, i32 0
+ %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
%3 = icmp ult <8 x i32> %1, %2
%4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
ret <8 x i32> %4
}
-define <8 x i16> @max_lt_v8i16c() {
-; SSE2-LABEL: max_lt_v8i16c:
+define <8 x i16> @min_lt_v8i16c() {
+; SSE2-LABEL: min_lt_v8i16c:
; SSE2: # BB#0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65529,65531,65533,65535,1,3,5,7]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: retq
;
-; SSE41-LABEL: max_lt_v8i16c:
+; SSE41-LABEL: min_lt_v8i16c:
; SSE41: # BB#0:
-; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
-; SSE41-NEXT: pminuw {{.*}}(%rip), %xmm0
+; SSE41-NEXT: movaps {{.*#+}} xmm0 = [1,65531,65531,65529,1,3,3,1]
; SSE41-NEXT: retq
;
-; SSE42-LABEL: max_lt_v8i16c:
+; SSE42-LABEL: min_lt_v8i16c:
; SSE42: # BB#0:
-; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
-; SSE42-NEXT: pminuw {{.*}}(%rip), %xmm0
+; SSE42-NEXT: movaps {{.*#+}} xmm0 = [1,65531,65531,65529,1,3,3,1]
; SSE42-NEXT: retq
;
-; AVX-LABEL: max_lt_v8i16c:
+; AVX-LABEL: min_lt_v8i16c:
; AVX: # BB#0:
-; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
-; AVX-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1,65531,65531,65529,1,3,3,1]
; AVX-NEXT: retq
- %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i16 0
- %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 1, i16 0
+ %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
+ %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 1, i32 0
%3 = icmp ult <8 x i16> %1, %2
%4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
ret <8 x i16> %4
}
-define <16 x i16> @max_lt_v16i16c() {
-; SSE2-LABEL: max_lt_v16i16c:
+define <16 x i16> @min_lt_v16i16c() {
+; SSE2-LABEL: min_lt_v16i16c:
; SSE2: # BB#0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [32775,32774,32773,32772,32771,32770,32769,32768]
; SSE2-NEXT: pcmpgtw {{.*}}(%rip), %xmm1
; SSE2-NEXT: por %xmm2, %xmm1
; SSE2-NEXT: retq
;
-; SSE41-LABEL: max_lt_v16i16c:
+; SSE41-LABEL: min_lt_v16i16c:
; SSE41: # BB#0:
-; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
-; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
-; SSE41-NEXT: pminuw {{.*}}(%rip), %xmm0
-; SSE41-NEXT: pminuw {{.*}}(%rip), %xmm1
+; SSE41-NEXT: movaps {{.*#+}} xmm0 = [1,65530,65531,65532,65531,65530,65529,0]
+; SSE41-NEXT: movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0]
; SSE41-NEXT: retq
;
-; SSE42-LABEL: max_lt_v16i16c:
+; SSE42-LABEL: min_lt_v16i16c:
; SSE42: # BB#0:
-; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
-; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
-; SSE42-NEXT: pminuw {{.*}}(%rip), %xmm0
-; SSE42-NEXT: pminuw {{.*}}(%rip), %xmm1
+; SSE42-NEXT: movaps {{.*#+}} xmm0 = [1,65530,65531,65532,65531,65530,65529,0]
+; SSE42-NEXT: movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0]
; SSE42-NEXT: retq
;
-; AVX1-LABEL: max_lt_v16i16c:
-; AVX1: # BB#0:
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
-; AVX1-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
-; AVX1-NEXT: vpminuw {{.*}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: max_lt_v16i16c:
-; AVX2: # BB#0:
-; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
-; AVX2-NEXT: vpminuw {{.*}}(%rip), %ymm0, %ymm0
-; AVX2-NEXT: retq
-;
-; AVX512-LABEL: max_lt_v16i16c:
-; AVX512: # BB#0:
-; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
-; AVX512-NEXT: vpminuw {{.*}}(%rip), %ymm0, %ymm0
-; AVX512-NEXT: retq
- %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i16 0
- %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 1, i16 0
+; AVX-LABEL: min_lt_v16i16c:
+; AVX: # BB#0:
+; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [1,65530,65531,65532,65531,65530,65529,0,1,2,3,4,3,2,1,0]
+; AVX-NEXT: retq
+ %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
+ %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 1, i32 0
%3 = icmp ult <16 x i16> %1, %2
%4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
ret <16 x i16> %4
}
-define <16 x i8> @max_lt_v16i8c() {
-; SSE-LABEL: max_lt_v16i8c:
+define <16 x i8> @min_lt_v16i8c() {
+; SSE-LABEL: min_lt_v16i8c:
; SSE: # BB#0:
-; SSE-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
-; SSE-NEXT: pminub {{.*}}(%rip), %xmm0
+; SSE-NEXT: movaps {{.*#+}} xmm0 = [1,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
; SSE-NEXT: retq
;
-; AVX-LABEL: max_lt_v16i8c:
+; AVX-LABEL: min_lt_v16i8c:
; AVX: # BB#0:
-; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
-; AVX-NEXT: vpminub {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
; AVX-NEXT: retq
- %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i8 0
- %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 1, i8 0
+ %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
+ %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 1, i32 0
%3 = icmp ult <16 x i8> %1, %2
%4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
ret <16 x i8> %4
}
-define <2 x i64> @max_le_v2i64c() {
-; SSE2-LABEL: max_le_v2i64c:
+define <2 x i64> @min_le_v2i64c() {
+; SSE2-LABEL: min_le_v2i64c:
; SSE2: # BB#0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [18446744073709551609,7]
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [18446744073709551615,1]
; SSE2-NEXT: por %xmm3, %xmm0
; SSE2-NEXT: retq
;
-; SSE41-LABEL: max_le_v2i64c:
+; SSE41-LABEL: min_le_v2i64c:
; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [18446744073709551609,7]
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [18446744073709551615,1]
; SSE41-NEXT: movapd %xmm1, %xmm0
; SSE41-NEXT: retq
;
-; SSE42-LABEL: max_le_v2i64c:
+; SSE42-LABEL: min_le_v2i64c:
; SSE42: # BB#0:
; SSE42-NEXT: movapd {{.*#+}} xmm1 = [18446744073709551615,1]
; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775801,9223372036854775815]
; SSE42-NEXT: movapd %xmm1, %xmm0
; SSE42-NEXT: retq
;
-; AVX-LABEL: max_le_v2i64c:
+; AVX-LABEL: min_le_v2i64c:
; AVX: # BB#0:
; AVX-NEXT: vmovapd {{.*#+}} xmm0 = [18446744073709551615,1]
; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775801,9223372036854775815]
ret <2 x i64> %4
}
-define <4 x i64> @max_le_v4i64c() {
-; SSE2-LABEL: max_le_v4i64c:
+define <4 x i64> @min_le_v4i64c() {
+; SSE2-LABEL: min_le_v4i64c:
; SSE2: # BB#0:
; SSE2-NEXT: movdqa {{.*#+}} xmm10 = [18446744073709551609,18446744073709551615]
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [1,7]
; SSE2-NEXT: por %xmm6, %xmm1
; SSE2-NEXT: retq
;
-; SSE41-LABEL: max_le_v4i64c:
+; SSE41-LABEL: min_le_v4i64c:
; SSE41: # BB#0:
; SSE41-NEXT: movdqa {{.*#+}} xmm9 = [18446744073709551609,18446744073709551615]
; SSE41-NEXT: movdqa {{.*#+}} xmm8 = [1,7]
; SSE41-NEXT: movapd %xmm2, %xmm0
; SSE41-NEXT: retq
;
-; SSE42-LABEL: max_le_v4i64c:
+; SSE42-LABEL: min_le_v4i64c:
; SSE42: # BB#0:
; SSE42-NEXT: movapd {{.*#+}} xmm1 = [7,1]
; SSE42-NEXT: movapd {{.*#+}} xmm2 = [18446744073709551615,18446744073709551609]
; SSE42-NEXT: movapd %xmm2, %xmm0
; SSE42-NEXT: retq
;
-; AVX1-LABEL: max_le_v4i64c:
+; AVX1-LABEL: min_le_v4i64c:
; AVX1: # BB#0:
; AVX1-NEXT: vmovapd {{.*#+}} ymm0 = [18446744073709551615,18446744073709551609,7,1]
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775809,9223372036854775815]
; AVX1-NEXT: vblendvpd %ymm1, {{.*}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq
;
-; AVX2-LABEL: max_le_v4i64c:
+; AVX2-LABEL: min_le_v4i64c:
; AVX2: # BB#0:
; AVX2-NEXT: vmovapd {{.*#+}} ymm0 = [18446744073709551615,18446744073709551609,7,1]
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [9223372036854775801,9223372036854775807,9223372036854775809,9223372036854775815]
; AVX2-NEXT: vblendvpd %ymm1, {{.*}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
-; AVX512-LABEL: max_le_v4i64c:
+; AVX512-LABEL: min_le_v4i64c:
; AVX512: # BB#0:
; AVX512-NEXT: vmovapd {{.*#+}} ymm0 = [18446744073709551615,18446744073709551609,7,1]
; AVX512-NEXT: vmovdqa {{.*#+}} ymm1 = [9223372036854775801,9223372036854775807,9223372036854775809,9223372036854775815]
ret <4 x i64> %4
}
-define <4 x i32> @max_le_v4i32c() {
-; SSE2-LABEL: max_le_v4i32c:
+define <4 x i32> @min_le_v4i32c() {
+; SSE2-LABEL: min_le_v4i32c:
; SSE2: # BB#0:
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [2147483641,2147483647,2147483649,2147483655]
; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: retq
;
-; SSE41-LABEL: max_le_v4i32c:
+; SSE41-LABEL: min_le_v4i32c:
; SSE41: # BB#0:
-; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
-; SSE41-NEXT: pminud {{.*}}(%rip), %xmm0
+; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
; SSE41-NEXT: retq
;
-; SSE42-LABEL: max_le_v4i32c:
+; SSE42-LABEL: min_le_v4i32c:
; SSE42: # BB#0:
-; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
-; SSE42-NEXT: pminud {{.*}}(%rip), %xmm0
+; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
; SSE42-NEXT: retq
;
-; AVX-LABEL: max_le_v4i32c:
+; AVX-LABEL: min_le_v4i32c:
; AVX: # BB#0:
-; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967295,1,7]
-; AVX-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
; AVX-NEXT: retq
%1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
- %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 1, i32 0
+ %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
%3 = icmp ule <4 x i32> %1, %2
%4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
ret <4 x i32> %4
}
-define <8 x i32> @max_le_v8i32c() {
-; SSE2-LABEL: max_le_v8i32c:
+define <8 x i32> @min_le_v8i32c() {
+; SSE2-LABEL: min_le_v8i32c:
; SSE2: # BB#0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483649,2147483651,2147483653,2147483655]
; SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
; SSE2-NEXT: por %xmm3, %xmm1
; SSE2-NEXT: retq
;
-; SSE41-LABEL: max_le_v8i32c:
+; SSE41-LABEL: min_le_v8i32c:
; SSE41: # BB#0:
-; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
-; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
-; SSE41-NEXT: pminud {{.*}}(%rip), %xmm0
-; SSE41-NEXT: pminud {{.*}}(%rip), %xmm1
+; SSE41-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
+; SSE41-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
; SSE41-NEXT: retq
;
-; SSE42-LABEL: max_le_v8i32c:
+; SSE42-LABEL: min_le_v8i32c:
; SSE42: # BB#0:
-; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,3,5,7]
-; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
-; SSE42-NEXT: pminud {{.*}}(%rip), %xmm0
-; SSE42-NEXT: pminud {{.*}}(%rip), %xmm1
+; SSE42-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
+; SSE42-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
; SSE42-NEXT: retq
;
-; AVX1-LABEL: max_le_v8i32c:
-; AVX1: # BB#0:
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967289,4294967291,4294967293,4294967295]
-; AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,3,5,7]
-; AVX1-NEXT: vpminud {{.*}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: max_le_v8i32c:
-; AVX2: # BB#0:
-; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
-; AVX2-NEXT: vpminud {{.*}}(%rip), %ymm0, %ymm0
-; AVX2-NEXT: retq
-;
-; AVX512-LABEL: max_le_v8i32c:
-; AVX512: # BB#0:
-; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [4294967289,4294967291,4294967293,4294967295,1,3,5,7]
-; AVX512-NEXT: vpminud {{.*}}(%rip), %ymm0, %ymm0
-; AVX512-NEXT: retq
+; AVX-LABEL: min_le_v8i32c:
+; AVX: # BB#0:
+; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
+; AVX-NEXT: retq
%1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
- %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 1, i32 0
+ %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
%3 = icmp ule <8 x i32> %1, %2
%4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
ret <8 x i32> %4
}
-define <8 x i16> @max_le_v8i16c() {
-; SSE2-LABEL: max_le_v8i16c:
+define <8 x i16> @min_le_v8i16c() {
+; SSE2-LABEL: min_le_v8i16c:
; SSE2: # BB#0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65529,65531,65533,65535,1,3,5,7]
-; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [1,65533,65531,65529,7,5,3,1]
+; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [65535,65533,65531,65529,7,5,3,1]
; SSE2-NEXT: movdqa %xmm1, %xmm3
; SSE2-NEXT: psubusw %xmm2, %xmm3
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: retq
;
-; SSE41-LABEL: max_le_v8i16c:
+; SSE41-LABEL: min_le_v8i16c:
; SSE41: # BB#0:
-; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
-; SSE41-NEXT: pminuw {{.*}}(%rip), %xmm0
+; SSE41-NEXT: movaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
; SSE41-NEXT: retq
;
-; SSE42-LABEL: max_le_v8i16c:
+; SSE42-LABEL: min_le_v8i16c:
; SSE42: # BB#0:
-; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
-; SSE42-NEXT: pminuw {{.*}}(%rip), %xmm0
+; SSE42-NEXT: movaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
; SSE42-NEXT: retq
;
-; AVX-LABEL: max_le_v8i16c:
+; AVX-LABEL: min_le_v8i16c:
; AVX: # BB#0:
-; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65531,65533,65535,1,3,5,7]
-; AVX-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
; AVX-NEXT: retq
- %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i16 0
- %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 1, i16 0
+ %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
+ %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
%3 = icmp ule <8 x i16> %1, %2
%4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
ret <8 x i16> %4
}
-define <16 x i16> @max_le_v16i16c() {
-; SSE2-LABEL: max_le_v16i16c:
+define <16 x i16> @min_le_v16i16c() {
+; SSE2-LABEL: min_le_v16i16c:
; SSE2: # BB#0:
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [65529,65530,65531,65532,65533,65534,65535,0]
; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [1,2,3,4,5,6,7,8]
-; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [1,65534,65533,65532,65531,65530,65529,0]
+; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [65535,65534,65533,65532,65531,65530,65529,0]
; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [7,6,5,4,3,2,1,0]
; SSE2-NEXT: movdqa %xmm3, %xmm1
; SSE2-NEXT: psubusw %xmm5, %xmm1
; SSE2-NEXT: por %xmm3, %xmm1
; SSE2-NEXT: retq
;
-; SSE41-LABEL: max_le_v16i16c:
+; SSE41-LABEL: min_le_v16i16c:
; SSE41: # BB#0:
-; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
-; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
-; SSE41-NEXT: pminuw {{.*}}(%rip), %xmm0
-; SSE41-NEXT: pminuw {{.*}}(%rip), %xmm1
+; SSE41-NEXT: movaps {{.*#+}} xmm0 = [65529,65530,65531,65532,65531,65530,65529,0]
+; SSE41-NEXT: movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0]
; SSE41-NEXT: retq
;
-; SSE42-LABEL: max_le_v16i16c:
+; SSE42-LABEL: min_le_v16i16c:
; SSE42: # BB#0:
-; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
-; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
-; SSE42-NEXT: pminuw {{.*}}(%rip), %xmm0
-; SSE42-NEXT: pminuw {{.*}}(%rip), %xmm1
+; SSE42-NEXT: movaps {{.*#+}} xmm0 = [65529,65530,65531,65532,65531,65530,65529,0]
+; SSE42-NEXT: movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0]
; SSE42-NEXT: retq
;
-; AVX1-LABEL: max_le_v16i16c:
-; AVX1: # BB#0:
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = [65529,65530,65531,65532,65533,65534,65535,0]
-; AVX1-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,3,4,5,6,7,8]
-; AVX1-NEXT: vpminuw {{.*}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: max_le_v16i16c:
-; AVX2: # BB#0:
-; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
-; AVX2-NEXT: vpminuw {{.*}}(%rip), %ymm0, %ymm0
-; AVX2-NEXT: retq
-;
-; AVX512-LABEL: max_le_v16i16c:
-; AVX512: # BB#0:
-; AVX512-NEXT: vmovdqa {{.*#+}} ymm0 = [65529,65530,65531,65532,65533,65534,65535,0,1,2,3,4,5,6,7,8]
-; AVX512-NEXT: vpminuw {{.*}}(%rip), %ymm0, %ymm0
-; AVX512-NEXT: retq
- %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i16 0
- %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 1, i16 0
+; AVX-LABEL: min_le_v16i16c:
+; AVX: # BB#0:
+; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65529,65530,65531,65532,65531,65530,65529,0,1,2,3,4,3,2,1,0]
+; AVX-NEXT: retq
+ %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
+ %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
%3 = icmp ule <16 x i16> %1, %2
%4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
ret <16 x i16> %4
}
-define <16 x i8> @max_le_v16i8c() {
-; SSE-LABEL: max_le_v16i8c:
+define <16 x i8> @min_le_v16i8c() {
+; SSE-LABEL: min_le_v16i8c:
; SSE: # BB#0:
-; SSE-NEXT: movdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
-; SSE-NEXT: pminub {{.*}}(%rip), %xmm0
+; SSE-NEXT: movaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
; SSE-NEXT: retq
;
-; AVX-LABEL: max_le_v16i8c:
+; AVX-LABEL: min_le_v16i8c:
; AVX: # BB#0:
-; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [249,250,251,252,253,254,255,0,1,2,3,4,5,6,7,8]
-; AVX-NEXT: vpminub {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
; AVX-NEXT: retq
- %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i8 0
- %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 1, i8 0
+ %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
+ %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
%3 = icmp ule <16 x i8> %1, %2
%4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
ret <16 x i8> %4