Tighten a ARM dag combine condition to avoid an identity transformation, which

[oota-llvm.git] / test / CodeGen / X86 / vec_insert-7.ll

diff --git a/test/CodeGen/X86/vec_insert-7.ll b/test/CodeGen/X86/vec_insert-7.ll
index 4dbed71a616974fa4ea39518966ad45f676c477b..268b5c4bf9721b6c22bd8f8850e7aaa660d0665c 100644 (file)
--- a/test/CodeGen/X86/vec_insert-7.ll
+++ b/test/CodeGen/X86/vec_insert-7.ll
@@ -1,9 +1,10 @@
-; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 -mtriple=i686-apple-darwin9 | FileCheck %s
+; RUN: llc < %s -march=x86 -mattr=+mmx,+sse42 -mtriple=i686-apple-darwin9 | FileCheck %s
 ; MMX insertelement is not available; these are promoted to XMM.
 ; (Without SSE they are split to two ints, and the code is much better.)
 
 define x86_mmx @mmx_movzl(x86_mmx %x) nounwind  {
 entry:
+; CHECK: mmx_movzl
 ; CHECK: pinsrd
 ; CHECK: pinsrd
         %tmp = bitcast x86_mmx %x to <2 x i32>