; BranchFolding should tail-merge the stores since they all precede
; direct branches to the same place.
-; CHECK: tail_merge_me:
+; CHECK-LABEL: tail_merge_me:
; CHECK-NOT: GHJK
; CHECK: movl $0, GHJK(%rip)
; CHECK-NEXT: movl $1, HABC(%rip)
; BranchFolding should tail-duplicate the indirect jump to avoid
; redundant branching.
-; CHECK: tail_duplicate_me:
+; CHECK-LABEL: tail_duplicate_me:
; CHECK: movl $0, GHJK(%rip)
; CHECK-NEXT: jmpq *%r
; CHECK: movl $0, GHJK(%rip)
; BranchFolding shouldn't try to merge the tails of two blocks
; with only a branch in common, regardless of the fallthrough situation.
-; CHECK: dont_merge_oddly:
+; CHECK-LABEL: dont_merge_oddly:
; CHECK-NOT: ret
-; CHECK: ucomiss %xmm1, %xmm2
+; CHECK: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}}
; CHECK-NEXT: jbe .LBB2_3
-; CHECK-NEXT: ucomiss %xmm0, %xmm1
+; CHECK-NEXT: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}}
; CHECK-NEXT: ja .LBB2_4
-; CHECK-NEXT: .LBB2_2:
-; CHECK-NEXT: movb $1, %al
-; CHECK-NEXT: ret
+; CHECK-NEXT: jmp .LBB2_2
; CHECK-NEXT: .LBB2_3:
-; CHECK-NEXT: ucomiss %xmm0, %xmm2
+; CHECK-NEXT: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}}
; CHECK-NEXT: jbe .LBB2_2
; CHECK-NEXT: .LBB2_4:
-; CHECK-NEXT: xorb %al, %al
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB2_2:
+; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: ret
define i1 @dont_merge_oddly(float* %result) nounwind {
; Do any-size tail-merging when two candidate blocks will both require
; an unconditional jump to complete a two-way conditional branch.
-; CHECK: c_expand_expr_stmt:
-; CHECK: jmp .LBB3_7
-; CHECK-NEXT: .LBB3_12:
-; CHECK-NEXT: movq 8(%rax), %rax
-; CHECK-NEXT: movb 16(%rax), %al
-; CHECK-NEXT: cmpb $16, %al
-; CHECK-NEXT: je .LBB3_6
-; CHECK-NEXT: cmpb $23, %al
-; CHECK-NEXT: je .LBB3_6
-; CHECK-NEXT: jmp .LBB3_15
-; CHECK-NEXT: .LBB3_14:
-; CHECK-NEXT: cmpb $23, %bl
-; CHECK-NEXT: jne .LBB3_15
-; CHECK-NEXT: .LBB3_15:
+; CHECK-LABEL: c_expand_expr_stmt:
+;
+; This test only works when register allocation happens to use %rax for both
+; load addresses.
+;
+; CHE: jmp .LBB3_11
+; CHE-NEXT: .LBB3_9:
+; CHE-NEXT: movq 8(%rax), %rax
+; CHE-NEXT: xorl %edx, %edx
+; CHE-NEXT: movb 16(%rax), %al
+; CHE-NEXT: cmpb $16, %al
+; CHE-NEXT: je .LBB3_11
+; CHE-NEXT: cmpb $23, %al
+; CHE-NEXT: jne .LBB3_14
+; CHE-NEXT: .LBB3_11:
%0 = type { %struct.rtx_def* }
%struct.lang_decl = type opaque
; instructions are involved. This function should have only
; one ret instruction.
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: callq func
; CHECK-NEXT: .LBB4_2:
-; CHECK-NEXT: addq $8, %rsp
+; CHECK-NEXT: popq
; CHECK-NEXT: ret
define void @foo(i1* %V) nounwind {
; one - One instruction may be tail-duplicated even with optsize.
-; CHECK: one:
+; CHECK-LABEL: one:
; CHECK: movl $0, XYZ(%rip)
; CHECK: movl $0, XYZ(%rip)
]
bb7:
- volatile store i32 0, i32* @XYZ
+ store volatile i32 0, i32* @XYZ
unreachable
bbx:
]
bb12:
- volatile store i32 0, i32* @XYZ
+ store volatile i32 0, i32* @XYZ
unreachable
return:
; tail instead of one. This is too much to be merged, given
; the optsize attribute.
-; CHECK: two:
+; CHECK-LABEL: two:
; CHECK-NOT: XYZ
+; CHECK: ret
; CHECK: movl $0, XYZ(%rip)
; CHECK: movl $1, XYZ(%rip)
; CHECK-NOT: XYZ
-; CHECK: ret
define void @two() nounwind optsize {
entry:
]
bb7:
- volatile store i32 0, i32* @XYZ
- volatile store i32 1, i32* @XYZ
+ store volatile i32 0, i32* @XYZ
+ store volatile i32 1, i32* @XYZ
unreachable
bbx:
]
bb12:
- volatile store i32 0, i32* @XYZ
- volatile store i32 1, i32* @XYZ
+ store volatile i32 0, i32* @XYZ
+ store volatile i32 1, i32* @XYZ
unreachable
return:
; two_nosize - Same as two, but without the optsize attribute.
; Now two instructions are enough to be tail-duplicated.
-; CHECK: two_nosize:
+; CHECK-LABEL: two_nosize:
; CHECK: movl $0, XYZ(%rip)
; CHECK: movl $1, XYZ(%rip)
; CHECK: movl $0, XYZ(%rip)
]
bb7:
- volatile store i32 0, i32* @XYZ
- volatile store i32 1, i32* @XYZ
+ store volatile i32 0, i32* @XYZ
+ store volatile i32 1, i32* @XYZ
unreachable
bbx:
]
bb12:
- volatile store i32 0, i32* @XYZ
- volatile store i32 1, i32* @XYZ
+ store volatile i32 0, i32* @XYZ
+ store volatile i32 1, i32* @XYZ
unreachable
return:
; Tail-merging should merge the two ret instructions since one side
; can fall-through into the ret and the other side has to branch anyway.
-; CHECK: TESTE:
-; CHECK: imulq
-; CHECK-NEXT: LBB8_2:
-; CHECK-NEXT: ret
+; CHECK-LABEL: TESTE:
+; CHECK: ret
+; CHECK-NOT: ret
+; CHECK: size TESTE
define i64 @TESTE(i64 %parami, i64 %paraml) nounwind readnone {
entry: