Fix a broadcast related regression on the vector shuffle lowering.

[oota-llvm.git] / test / CodeGen / X86 / store_op_load_fold2.ll

diff --git a/test/CodeGen/X86/store_op_load_fold2.ll b/test/CodeGen/X86/store_op_load_fold2.ll
index 3c2c31182c2f12c092742d646064d374c2c6079a..705fdcdc13af55863ded55ea3b4f2f63d79b5f61 100644 (file)
--- a/test/CodeGen/X86/store_op_load_fold2.ll
+++ b/test/CodeGen/X86/store_op_load_fold2.ll
@@ -1,46 +1,30 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | grep 'and DWORD PTR' | wc -l | grep 1
-;
-; FIXME: The number of (store (and (load ..) ..) ..) really should be 2. But the current hack
-; only allow one of the folding to happen.
-; XFAIL: *
+; RUN: llc < %s -mtriple=i686-linux -mcpu=corei7 -x86-asm-syntax=att | FileCheck %s -check-prefix=ATT
+; RUN: llc < %s -mtriple=i686-linux -mcpu=corei7 -x86-asm-syntax=intel | FileCheck %s -check-prefix=INTEL
+
+target datalayout = "e-p:32:32"
+        %struct.Macroblock = type { i32, i32, i32, i32, i32, [8 x i32], %struct.Macroblock*, %struct.Macroblock*, i32, [2 x [4 x [4 x [2 x i32]]]], [16 x i8], [16 x i8], i32, i64, [4 x i32], [4 x i32], i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i16, double, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+
+define internal fastcc i32 @dct_chroma(i32 %uv, i32 %cr_cbp) nounwind {
+cond_true2732.preheader:                ; preds = %entry
+        %tmp2666 = getelementptr %struct.Macroblock* null, i32 0, i32 13                ; <i64*> [#uses=2]
+        %tmp2674 = trunc i32 0 to i8            ; <i8> [#uses=1]
+        %tmp2667.us.us = load i64* %tmp2666             ; <i64> [#uses=1]
+        %tmp2670.us.us = load i64* null         ; <i64> [#uses=1]
+        %shift.upgrd.1 = zext i8 %tmp2674 to i64                ; <i64> [#uses=1]
+        %tmp2675.us.us = shl i64 %tmp2670.us.us, %shift.upgrd.1         ; <i64> [#uses=1]
+        %tmp2675not.us.us = xor i64 %tmp2675.us.us, -1          ; <i64> [#uses=1]
+        %tmp2676.us.us = and i64 %tmp2667.us.us, %tmp2675not.us.us              ; <i64> [#uses=1]
+        store i64 %tmp2676.us.us, i64* %tmp2666
+        ret i32 0
+
+; INTEL:       and     {{e..}}, dword ptr [360]
+; INTEL:       and     dword ptr [356], {{e..}}
+; FIXME:       mov     dword ptr [360], {{e..}}
+; The above line comes out as 'mov 360, eax', but when the register is ecx it works?
+
+; ATT:         andl    360, %{{e..}}
+; ATT: andl    %{{e..}}, 356
+; ATT: movl    %{{e..}}, 360
 
-       %struct.Macroblock = type { int, int, int, int, int, [8 x int], %struct.Macroblock*, %struct.Macroblock*, int, [2 x [4 x [4 x [2 x int]]]], [16 x sbyte], [16 x sbyte], int, long, [4 x int], [4 x int], long, int, int, int, int, int, int, int, int, int, int, int, int, int, int, int, short, double, int, int, int, int, int, int, int, int, int }
-
-implementation   ; Functions:
-
-internal fastcc int %dct_chroma(int %uv, int %cr_cbp) {
-entry:
-       br bool false, label %bb2611, label %cond_true129
-
-cond_true129:          ; preds = %entry
-       ret int 0
-
-bb2611:                ; preds = %entry
-       br bool false, label %cond_true2732.preheader, label %cond_next2752
-
-cond_true2732.preheader:               ; preds = %bb2611
-       %tmp2666 = getelementptr %struct.Macroblock* null, int 0, uint 13               ; <long*> [#uses=2]
-       %tmp2674 = cast int 0 to ubyte          ; <ubyte> [#uses=1]
-       br bool false, label %cond_true2732.preheader.split.us, label %cond_true2732.preheader.split
-
-cond_true2732.preheader.split.us:              ; preds = %cond_true2732.preheader
-       br bool false, label %cond_true2732.outer.us.us, label %cond_true2732.outer.us
-
-cond_true2732.outer.us.us:             ; preds = %cond_true2732.preheader.split.us
-       %tmp2667.us.us = load long* %tmp2666            ; <long> [#uses=1]
-       %tmp2670.us.us = load long* null                ; <long> [#uses=1]
-       %tmp2675.us.us = shl long %tmp2670.us.us, ubyte %tmp2674                ; <long> [#uses=1]
-       %tmp2675not.us.us = xor long %tmp2675.us.us, -1         ; <long> [#uses=1]
-       %tmp2676.us.us = and long %tmp2667.us.us, %tmp2675not.us.us             ; <long> [#uses=1]
-       store long %tmp2676.us.us, long* %tmp2666
-       ret int 0
-
-cond_true2732.outer.us:                ; preds = %cond_true2732.preheader.split.us
-       ret int 0
-
-cond_true2732.preheader.split:         ; preds = %cond_true2732.preheader
-       ret int 0
-
-cond_next2752:         ; preds = %bb2611
-       ret int 0
 }
+