If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM registers...

[oota-llvm.git] / test / CodeGen / X86 / sse-align-8.ll

diff --git a/test/CodeGen/X86/sse-align-8.ll b/test/CodeGen/X86/sse-align-8.ll
index 4353698dcc03dbf7d2425d59c8a3f178fd5a9385..17a3d2987fff26354ce59c84f62e3d6691a97eac 100644 (file)
--- a/test/CodeGen/X86/sse-align-8.ll
+++ b/test/CodeGen/X86/sse-align-8.ll
@@ -1,7 +1,6 @@
 ; RUN: llvm-as < %s | llc -march=x86-64 | grep movups | count 1
 
-define void @bar(<2 x i64>* %p, <2 x i64> %x)
-{
+define void @bar(<2 x i64>* %p, <2 x i64> %x) nounwind {
   store <2 x i64> %x, <2 x i64>* %p, align 8
   ret void
 }