Allow AVX vrsqrtps generation.

[oota-llvm.git] / test / CodeGen / X86 / sqrt-fastmath.ll

diff --git a/test/CodeGen/X86/sqrt-fastmath.ll b/test/CodeGen/X86/sqrt-fastmath.ll
index 65f719e4e1721bcbe6b7238ec2251e3362b29067..24b175eed7a3c8faecec0f278fa28fa4649f345b 100644 (file)
--- a/test/CodeGen/X86/sqrt-fastmath.ll
+++ b/test/CodeGen/X86/sqrt-fastmath.ll
@@ -55,9 +55,14 @@ entry:
 
 declare x86_fp80 @__sqrtl_finite(x86_fp80) #1
 
+declare float @llvm.sqrt.f32(float) #1
+declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #1
+declare <8 x float> @llvm.sqrt.v8f32(<8 x float>) #1
+
 ; If the target's sqrtss and divss instructions are substantially
 ; slower than rsqrtss with a Newton-Raphson refinement, we should
 ; generate the estimate sequence.
+
 define float @reciprocal_square_root(float %x) #0 {
   %sqrt = tail call float @llvm.sqrt.f32(float %x)
   %div = fdiv fast float 1.0, %sqrt
@@ -78,11 +83,6 @@ define float @reciprocal_square_root(float %x) #0 {
 ; BTVER2-NEXT: retq
 }
 
-declare float @llvm.sqrt.f32(float) #1
-
-; If the target's sqrtps and divps instructions are substantially
-; slower than rsqrtps with a Newton-Raphson refinement, we should
-; generate the estimate sequence.
 define <4 x float> @reciprocal_square_root_v4f32(<4 x float> %x) #0 {
   %sqrt = tail call <4 x float> @llvm.sqrt.v4f32(<4 x float> %x)
   %div = fdiv fast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, %sqrt
@@ -103,7 +103,28 @@ define <4 x float> @reciprocal_square_root_v4f32(<4 x float> %x) #0 {
 ; BTVER2-NEXT: retq
 }
 
-declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #1
+define <8 x float> @reciprocal_square_root_v8f32(<8 x float> %x) #0 {
+  %sqrt = tail call <8 x float> @llvm.sqrt.v8f32(<8 x float> %x)
+  %div = fdiv fast <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %sqrt
+  ret <8 x float> %div
+
+; CHECK-LABEL: reciprocal_square_root_v8f32:
+; CHECK: sqrtps
+; CHECK-NEXT: sqrtps
+; CHECK-NEXT: movaps
+; CHECK-NEXT: movaps
+; CHECK-NEXT: divps
+; CHECK-NEXT: divps
+; CHECK-NEXT: retq
+; BTVER2-LABEL: reciprocal_square_root_v8f32:
+; BTVER2: vrsqrtps
+; BTVER2-NEXT: vmulps
+; BTVER2-NEXT: vmulps
+; BTVER2-NEXT: vmulps
+; BTVER2-NEXT: vaddps
+; BTVER2-NEXT: vmulps
+; BTVER2-NEXT: retq
+}
 
 
 attributes #0 = { nounwind readnone uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "unsafe-fp-math"="true" "use-soft-float"="false" }