[x86] Simplify vector selection if condition value type matches vselect value type...

[oota-llvm.git] / test / CodeGen / X86 / smul-with-overflow.ll

diff --git a/test/CodeGen/X86/smul-with-overflow.ll b/test/CodeGen/X86/smul-with-overflow.ll
index 7ac3840482a23912f1886eaa9673014aa7a1670f..cefbda64751b6041fd5674f42a4dcaccd7623867 100644 (file)
--- a/test/CodeGen/X86/smul-with-overflow.ll
+++ b/test/CodeGen/X86/smul-with-overflow.ll
@@ -17,7 +17,7 @@ normal:
 overflow:
   %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
   ret i1 false
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: imull
 ; CHECK-NEXT: jno
 }
@@ -36,7 +36,7 @@ overflow:
 normal:
   %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
   ret i1 true
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: imull
 ; CHECK-NEXT: jno
 }
@@ -50,7 +50,7 @@ entry:
        %tmp1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %tmp0, i32 2)
        %tmp2 = extractvalue { i32, i1 } %tmp1, 0
        ret i32 %tmp2
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: addl
 ; CHECK-NEXT: addl
 ; CHECK-NEXT: ret
@@ -62,8 +62,22 @@ entry:
        %tmp1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %tmp0, i32 4)
        %tmp2 = extractvalue { i32, i1 } %tmp1, 0
        ret i32 %tmp2
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: addl
 ; CHECK: mull
 ; CHECK-NEXT: ret
 }
+
+declare { i63, i1 } @llvm.smul.with.overflow.i63(i63, i63) nounwind readnone
+
+define i1 @test5() nounwind {
+entry:
+  %res = call { i63, i1 } @llvm.smul.with.overflow.i63(i63 4, i63 4611686018427387903)
+  %sum = extractvalue { i63, i1 } %res, 0
+  %overflow = extractvalue { i63, i1 } %res, 1
+  ret i1 %overflow
+; Was returning false, should return true (not constant folded yet though).
+; PR13991
+; CHECK-LABEL: test5:
+; CHECK-NOT: xorb
+}