[X86][SSE] Vectorized i8 and i16 shift operators

[oota-llvm.git] / test / CodeGen / X86 / shift-folding.ll

diff --git a/test/CodeGen/X86/shift-folding.ll b/test/CodeGen/X86/shift-folding.ll
index 19bf4ee6480c80f1d133d0d53da3d2382dabfff1..69887870897785ffcb9cac66b0c55ea40a656116 100644 (file)
--- a/test/CodeGen/X86/shift-folding.ll
+++ b/test/CodeGen/X86/shift-folding.ll
@@ -1,20 +1,70 @@
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=x86 | \
-; RUN:   grep {s\[ah\]\[rl\]l} | count 1
+; RUN: llc < %s -march=x86 -verify-coalescing | FileCheck %s
 
-int* %test1(int *%P, uint %X) {
-       %Y = shr uint %X, ubyte 2
-       %P2 = getelementptr int* %P, uint %Y
-       ret int* %P2
+define i32* @test1(i32* %P, i32 %X) {
+; CHECK-LABEL: test1:
+; CHECK-NOT: shrl
+; CHECK-NOT: shll
+; CHECK: ret
+
+entry:
+  %Y = lshr i32 %X, 2
+  %gep.upgrd.1 = zext i32 %Y to i64
+  %P2 = getelementptr i32, i32* %P, i64 %gep.upgrd.1
+  ret i32* %P2
 }
 
-int* %test2(int *%P, uint %X) {
-       %Y = shl uint %X, ubyte 2
-       %P2 = getelementptr int* %P, uint %Y
-       ret int* %P2
+define i32* @test2(i32* %P, i32 %X) {
+; CHECK-LABEL: test2:
+; CHECK: shll $4
+; CHECK-NOT: shll
+; CHECK: ret
+
+entry:
+  %Y = shl i32 %X, 2
+  %gep.upgrd.2 = zext i32 %Y to i64
+  %P2 = getelementptr i32, i32* %P, i64 %gep.upgrd.2
+  ret i32* %P2
+}
+
+define i32* @test3(i32* %P, i32 %X) {
+; CHECK-LABEL: test3:
+; CHECK-NOT: shrl
+; CHECK-NOT: shll
+; CHECK: ret
+
+entry:
+  %Y = ashr i32 %X, 2
+  %P2 = getelementptr i32, i32* %P, i32 %Y
+  ret i32* %P2
 }
 
-int* %test3(int *%P, int %X) {
-       %Y = shr int %X, ubyte 2
-       %P2 = getelementptr int* %P, int %Y
-       ret int* %P2
+define fastcc i32 @test4(i32* %d) {
+; CHECK-LABEL: test4:
+; CHECK-NOT: shrl
+; CHECK: ret
+
+entry:
+  %tmp4 = load i32, i32* %d
+  %tmp512 = lshr i32 %tmp4, 24
+  ret i32 %tmp512
+}
+
+define i64 @test5(i16 %i, i32* %arr) {
+; Ensure that we don't fold away shifts which have multiple uses, as they are
+; just re-introduced for the second use.
+; CHECK-LABEL: test5:
+; CHECK-NOT: shrl
+; CHECK: shrl $11
+; CHECK-NOT: shrl
+; CHECK: ret
+
+entry:
+  %i.zext = zext i16 %i to i32
+  %index = lshr i32 %i.zext, 11
+  %index.zext = zext i32 %index to i64
+  %val.ptr = getelementptr inbounds i32, i32* %arr, i64 %index.zext
+  %val = load i32, i32* %val.ptr
+  %val.zext = zext i32 %val to i64
+  %sum = add i64 %val.zext, %index.zext
+  ret i64 %sum
 }