llvm/test/CodeGen/X86/xor.ll: Appease Win32 targets since r240796.

[oota-llvm.git] / test / CodeGen / X86 / select.ll

diff --git a/test/CodeGen/X86/select.ll b/test/CodeGen/X86/select.ll
index cdd258d92031a9de23213ae462b041d2215fa8cf..a4e06b39844675255b3d3e0d028a3993836a729b 100644 (file)
--- a/test/CodeGen/X86/select.ll
+++ b/test/CodeGen/X86/select.ll
@@ -5,8 +5,8 @@
 %0 = type { i64, i32 }
 
 define i32 @test1(%0* %p, %0* %q, i1 %r) nounwind {
-  %t0 = load %0* %p
-  %t1 = load %0* %q
+  %t0 = load %0, %0* %p
+  %t1 = load %0, %0* %q
   %t4 = select i1 %r, %0 %t0, %0 %t1
   %t5 = extractvalue %0 %t4, 1
   ret i32 %t5
@@ -62,8 +62,8 @@ define signext i8 @test4(i8* nocapture %P, double %F) nounwind readonly {
 entry:
        %0 = fcmp olt double %F, 4.200000e+01           ; <i1> [#uses=1]
        %iftmp.0.0 = select i1 %0, i32 4, i32 0         ; <i32> [#uses=1]
-       %1 = getelementptr i8* %P, i32 %iftmp.0.0               ; <i8*> [#uses=1]
-       %2 = load i8* %1, align 1               ; <i8> [#uses=1]
+       %1 = getelementptr i8, i8* %P, i32 %iftmp.0.0           ; <i8*> [#uses=1]
+       %2 = load i8, i8* %1, align 1           ; <i8> [#uses=1]
        ret i8 %2
 ; CHECK-LABEL: test4:
 ; CHECK: movsbl        ({{.*}},4), %eax
@@ -82,8 +82,8 @@ define void @test5(i1 %c, <2 x i16> %a, <2 x i16> %b, <2 x i16>* %p) nounwind {
 }
 
 define void @test6(i32 %C, <4 x float>* %A, <4 x float>* %B) nounwind {
-        %tmp = load <4 x float>* %A             ; <<4 x float>> [#uses=1]
-        %tmp3 = load <4 x float>* %B            ; <<4 x float>> [#uses=2]
+        %tmp = load <4 x float>, <4 x float>* %A             ; <<4 x float>> [#uses=1]
+        %tmp3 = load <4 x float>, <4 x float>* %B            ; <<4 x float>> [#uses=2]
         %tmp9 = fmul <4 x float> %tmp3, %tmp3            ; <<4 x float>> [#uses=1]
         %tmp.upgrd.1 = icmp eq i32 %C, 0                ; <i1> [#uses=1]
         %iftmp.38.0 = select i1 %tmp.upgrd.1, <4 x float> %tmp9, <4 x float> %tmp               ; <<4 x float>> [#uses=1]
@@ -357,3 +357,47 @@ define i8 @test18(i32 %x, i8 zeroext %a, i8 zeroext %b) nounwind {
 ; ATOM: cmpl $15, %edi
 ; ATOM: cmovgel %edx
 }
+
+; CHECK-LABEL: @trunc_select_miscompile
+; CHECK-NOT: sarb
+define i32 @trunc_select_miscompile(i32 %a, i1 zeroext %cc) {
+  %tmp1 = select i1 %cc, i32 3, i32 2
+  %tmp2 = shl i32 %a, %tmp1
+  ret i32 %tmp2
+}
+
+define void @test19() {
+; This is a massive reduction of an llvm-stress test case that generates
+; interesting chains feeding setcc and eventually a f32 select operation. This
+; is intended to exercise the SELECT formation in the DAG combine simplifying
+; a simplified select_cc node. If it it regresses and is no longer triggering
+; that code path, it can be deleted.
+;
+; CHECK-LABEL: @test19
+; CHECK: testb
+; CHECK: cmpl
+; CHECK: ucomiss
+
+BB:
+  br label %CF
+
+CF:
+  %Cmp10 = icmp ule i8 undef, undef
+  br i1 %Cmp10, label %CF, label %CF250
+
+CF250:
+  %E12 = extractelement <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, i32 2
+  %Cmp32 = icmp ugt i1 %Cmp10, false
+  br i1 %Cmp32, label %CF, label %CF242
+
+CF242:
+  %Cmp38 = icmp uge i32 %E12, undef
+  %FC = uitofp i1 %Cmp38 to float
+  %Sl59 = select i1 %Cmp32, float %FC, float undef
+  %Cmp60 = fcmp ugt float undef, undef
+  br i1 %Cmp60, label %CF242, label %CF244
+
+CF244:
+  %B122 = fadd float %Sl59, undef
+  ret void
+}