Enable the new no-SP register classes by default. This is to address

[oota-llvm.git] / test / CodeGen / X86 / rem.ll

diff --git a/test/CodeGen/X86/rem.ll b/test/CodeGen/X86/rem.ll
index 209f831fc80aeeac01fd6aaaa9c04542d6466f9f..bba1f9b96bb4ee3e1c19f811385ab2d515251887 100644 (file)
--- a/test/CodeGen/X86/rem.ll
+++ b/test/CodeGen/X86/rem.ll
@@ -1,23 +1,22 @@
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=x86 &&
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=x86 | not grep div
+; RUN: llvm-as < %s | llc -march=x86 | not grep div
 
-int %test1(int %X) {
-        %tmp1 = rem int %X, 255
-        ret int %tmp1
+define i32 @test1(i32 %X) {
+        %tmp1 = srem i32 %X, 255                ; <i32> [#uses=1]
+        ret i32 %tmp1
 }
 
-int %test2(int %X) {
-        %tmp1 = rem int %X, 256 
-        ret int %tmp1
+define i32 @test2(i32 %X) {
+        %tmp1 = srem i32 %X, 256                ; <i32> [#uses=1]
+        ret i32 %tmp1
 }
 
-uint %test3(uint %X) {
-        %tmp1 = rem uint %X, 255
-        ret uint %tmp1
+define i32 @test3(i32 %X) {
+        %tmp1 = urem i32 %X, 255                ; <i32> [#uses=1]
+        ret i32 %tmp1
 }
 
-uint %test4(uint %X) {
-        %tmp1 = rem uint %X, 256  ; just an and
-        ret uint %tmp1
+define i32 @test4(i32 %X) {
+        %tmp1 = urem i32 %X, 256                ; <i32> [#uses=1]
+        ret i32 %tmp1
 }