[AVX512] Enabling bit logic lowering

[oota-llvm.git] / test / CodeGen / X86 / prefetch.ll

diff --git a/test/CodeGen/X86/prefetch.ll b/test/CodeGen/X86/prefetch.ll
index bcc6e3ad3dd2137bf2bbe9d5fa143e852a7fed50..d6571acbbb7e0864d7ba111d3afacd62da23ae46 100644 (file)
--- a/test/CodeGen/X86/prefetch.ll
+++ b/test/CodeGen/X86/prefetch.ll
@@ -1,15 +1,27 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse1 | grep prefetchnta
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse1 | grep prefetcht0
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse1 | grep prefetcht1
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse1 | grep prefetcht2
+; RUN: llc < %s -march=x86 -mattr=+sse | FileCheck %s
+; RUN: llc < %s -march=x86 -mattr=+avx | FileCheck %s
+; RUN: llc < %s -march=x86 -mattr=+sse -mattr=+prfchw | FileCheck %s -check-prefix=PRFCHW
+; RUN: llc < %s -march=x86 -mcpu=slm | FileCheck %s -check-prefix=SLM
+; RUN: llc < %s -march=x86 -mcpu=btver2 | FileCheck %s -check-prefix=PRFCHW
+; RUN: llc < %s -march=x86 -mcpu=btver2 -mattr=-prfchw | FileCheck %s -check-prefix=NOPRFCHW
+
+; rdar://10538297
 
 define void @t(i8* %ptr) nounwind  {
 entry:
-       tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1 )
-       tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2 )
-       tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3 )
-       tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 0 )
+; CHECK: prefetcht2
+; CHECK: prefetcht1
+; CHECK: prefetcht0
+; CHECK: prefetchnta
+; PRFCHW: prefetchw
+; NOPRFCHW-NOT: prefetchw
+; SLM: prefetchw
+       tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1, i32 1 )
+       tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2, i32 1 )
+       tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 1 )
+       tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 0, i32 1 )
+       tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3, i32 1 )
        ret void
 }
 
-declare void @llvm.prefetch(i8*, i32, i32) nounwind 
+declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind