ARM: spot SBFX-compatbile code expressed with sign_extend_inreg

[oota-llvm.git] / test / CodeGen / X86 / or-address.ll

diff --git a/test/CodeGen/X86/or-address.ll b/test/CodeGen/X86/or-address.ll
index 6447680e623bab94791d6db94e243f9ae157570a..6bea864027bd2d07b6e52ebdb5b00e0b8e85c241 100644 (file)
--- a/test/CodeGen/X86/or-address.ll
+++ b/test/CodeGen/X86/or-address.ll
@@ -4,10 +4,10 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 target triple = "x86_64-apple-darwin10.3"
 
 
-; CHECK:       movl    %{{.*}},   (%rdi,%rdx,4)
-; CHECK:       movl    %{{.*}},  8(%rdi,%rdx,4)
-; CHECK:       movl    %{{.*}},  4(%rdi,%rdx,4)
-; CHECK:       movl    %{{.*}}, 12(%rdi,%rdx,4)
+; CHECK:       movl    %{{.*}},   (%rdi,[[R0:.+]],4)
+; CHECK:       movl    %{{.*}},  8(%rdi,[[R0]],4)
+; CHECK:       movl    %{{.*}},  4(%rdi,[[R0]],4)
+; CHECK:       movl    %{{.*}}, 12(%rdi,[[R0]],4)
 
 define void @test(i32* nocapture %array, i32 %r0) nounwind ssp noredzone {
 bb.nph:
@@ -46,11 +46,11 @@ return:                                           ; preds = %bb
   ret void
 }
 
-; CHECK: test1:
-; CHECK:       movl    %{{.*}},   (%rdi,%rcx,4)
-; CHECK:       movl    %{{.*}},  8(%rdi,%rcx,4)
-; CHECK:       movl    %{{.*}},  4(%rdi,%rcx,4)
-; CHECK:       movl    %{{.*}}, 12(%rdi,%rcx,4)
+; CHECK-LABEL: test1:
+; CHECK:       movl    %{{.*}},   (%[[RDI:...]],%[[RCX:...]],4)
+; CHECK:       movl    %{{.*}},  8(%[[RDI]],%[[RCX]],4)
+; CHECK:       movl    %{{.*}},  4(%[[RDI]],%[[RCX]],4)
+; CHECK:       movl    %{{.*}}, 12(%[[RDI]],%[[RCX]],4)
 
 define void @test1(i32* nocapture %array, i32 %r0, i8 signext %k, i8 signext %i0) nounwind {
 bb.nph: