-; RUN: llc -asm-verbose=false -disable-branch-fold -disable-code-place -disable-tail-duplicate -march=x86-64 < %s | FileCheck %s
+; RUN: llc -asm-verbose=false -disable-branch-fold -disable-block-placement -disable-tail-duplicate -march=x86-64 -mcpu=nehalem -no-integrated-as < %s | FileCheck %s
; rdar://7236213
+;
+; The scheduler's 2-address hack has been disabled, so there is
+; currently no good guarantee that this test will pass until the
+; machine scheduler develops an equivalent heuristic.
; CodeGen shouldn't require any lea instructions inside the marked loop.
; It should properly set up post-increment uses and do coalescing for
return: ; preds = %entry
ret void
}
+
+; Codegen shouldn't crash on this testcase.
+
+define void @bar(i32 %a, i32 %b) nounwind {
+entry: ; preds = %bb1, %entry, %for.end204
+ br label %outer
+
+outer: ; preds = %bb1, %entry
+ %i6 = phi i32 [ %storemerge171, %bb1 ], [ %a, %entry ] ; <i32> [#uses=2]
+ %storemerge171 = add i32 %i6, 1 ; <i32> [#uses=1]
+ br label %inner
+
+inner: ; preds = %bb0, %if.end275
+ %i8 = phi i32 [ %a, %outer ], [ %indvar.next159, %bb0 ] ; <i32> [#uses=2]
+ %t338 = load i32* undef ; <i32> [#uses=1]
+ %t191 = mul i32 %i8, %t338 ; <i32> [#uses=1]
+ %t179 = add i32 %i6, %t191 ; <i32> [#uses=1]
+ br label %bb0
+
+bb0: ; preds = %for.body332
+ %indvar.next159 = add i32 %i8, 1 ; <i32> [#uses=1]
+ br i1 undef, label %bb1, label %inner
+
+bb1: ; preds = %bb0, %outer
+ %midx.4 = phi i32 [ %t179, %bb0 ] ; <i32> [#uses=0]
+ br label %outer
+}