[AVX512] Enabling bit logic lowering

[oota-llvm.git] / test / CodeGen / X86 / memset-2.ll

diff --git a/test/CodeGen/X86/memset-2.ll b/test/CodeGen/X86/memset-2.ll
index 2ad665cda75c4a9e69388759c93ad660fcf44c36..a87ef2e15a5a8c5648ce11f6b27541c8a138c68a 100644 (file)
--- a/test/CodeGen/X86/memset-2.ll
+++ b/test/CodeGen/X86/memset-2.ll
@@ -1,45 +1,39 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep rep
-; RUN: llvm-as < %s | llc -march=x86 | grep memset
+; RUN: llc -mtriple=i386-apple-darwin -mcpu=yonah < %s | FileCheck %s
 
 declare void @llvm.memset.i32(i8*, i8, i32, i32) nounwind
 
-define fastcc i32 @cli_scanzip(i32 %desc) nounwind {
+define fastcc void @t1() nounwind {
 entry:
-       br label %bb8.i.i.i.i
-
-bb8.i.i.i.i:           ; preds = %bb8.i.i.i.i, %entry
-       icmp eq i32 0, 0                ; <i1>:0 [#uses=1]
-       br i1 %0, label %bb61.i.i.i, label %bb8.i.i.i.i
-
-bb32.i.i.i:            ; preds = %bb61.i.i.i
-       ptrtoint i8* %tail.0.i.i.i to i32               ; <i32>:1 [#uses=1]
-       sub i32 0, %1           ; <i32>:2 [#uses=1]
-       icmp sgt i32 %2, 19             ; <i1>:3 [#uses=1]
-       br i1 %3, label %bb34.i.i.i, label %bb61.i.i.i
-
-bb34.i.i.i:            ; preds = %bb32.i.i.i
-       load i32* null, align 4         ; <i32>:4 [#uses=1]
-       icmp eq i32 %4, 101010256               ; <i1>:5 [#uses=1]
-       br i1 %5, label %bb8.i11.i.i.i, label %bb61.i.i.i
-
-bb8.i11.i.i.i:         ; preds = %bb8.i11.i.i.i, %bb34.i.i.i
-       icmp eq i32 0, 0                ; <i1>:6 [#uses=1]
-       br i1 %6, label %cli_dbgmsg.exit49.i, label %bb8.i11.i.i.i
+; CHECK-LABEL: t1:
+; CHECK: calll L_memset$stub
+  call void @llvm.memset.p0i8.i32(i8* null, i8 0, i32 188, i32 1, i1 false)
+  unreachable
+}
 
-cli_dbgmsg.exit49.i:           ; preds = %bb8.i11.i.i.i
-       icmp eq [32768 x i8]* null, null                ; <i1>:7 [#uses=1]
-       br i1 %7, label %bb1.i28.i, label %bb8.i.i
+define fastcc void @t2(i8 signext %c) nounwind {
+entry:
+; CHECK-LABEL: t2:
+; CHECK: calll L_memset$stub
+  call void @llvm.memset.p0i8.i32(i8* undef, i8 %c, i32 76, i32 1, i1 false)
+  unreachable
+}
 
-bb61.i.i.i:            ; preds = %bb61.i.i.i, %bb34.i.i.i, %bb32.i.i.i, %bb8.i.i.i.i
-       %tail.0.i.i.i = getelementptr [1024 x i8]* null, i32 0, i32 0           ; <i8*> [#uses=2]
-       load i8* %tail.0.i.i.i, align 1         ; <i8>:8 [#uses=1]
-       icmp eq i8 %8, 80               ; <i1>:9 [#uses=1]
-       br i1 %9, label %bb32.i.i.i, label %bb61.i.i.i
+declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind
 
-bb1.i28.i:             ; preds = %cli_dbgmsg.exit49.i
-       call void @llvm.memset.i32( i8* null, i8 0, i32 88, i32 1 ) nounwind
-       unreachable
+define void @t3(i8* nocapture %s, i8 %a) nounwind {
+entry:
+  tail call void @llvm.memset.p0i8.i32(i8* %s, i8 %a, i32 8, i32 1, i1 false)
+  ret void
+; CHECK-LABEL: t3:
+; CHECK: imull $16843009
+}
 
-bb8.i.i:               ; preds = %bb8.i.i, %cli_dbgmsg.exit49.i
-       br label %bb8.i.i
+define void @t4(i8* nocapture %s, i8 %a) nounwind {
+entry:
+  tail call void @llvm.memset.p0i8.i32(i8* %s, i8 %a, i32 15, i32 1, i1 false)
+  ret void
+; CHECK-LABEL: t4:
+; CHECK: imull $16843009
+; CHECK-NOT: imul
+; CHECK: ret
 }