[AVX512] Enabling bit logic lowering

[oota-llvm.git] / test / CodeGen / X86 / lower-vec-shift-2.ll

diff --git a/test/CodeGen/X86/lower-vec-shift-2.ll b/test/CodeGen/X86/lower-vec-shift-2.ll
index 90505b6dd8f30d05838c828cf8ce92d52e2a2686..770775d324277d85f07bfb9e3744b74cdea68cac 100644 (file)
--- a/test/CodeGen/X86/lower-vec-shift-2.ll
+++ b/test/CodeGen/X86/lower-vec-shift-2.ll
@@ -11,9 +11,8 @@ define <8 x i16> @test1(<8 x i16> %A, <8 x i16> %B) {
 ; SSE2-NEXT:    retq
 ; AVX-LABEL: test1:
 ; AVX:       # BB#0
-; AVX-NEXT:    vmovd  %xmm1, %eax
-; AVX-NEXT:    movzwl  %ax, %eax
-; AVX-NEXT:    vmovd  %eax, %xmm1
+; AVX-NEXT:    vpxor  %xmm2, %xmm2, %xmm2
+; AVX-NEXT:    vpblendw  {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
 ; AVX-NEXT:    vpsllw  %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    retq
 entry:
@@ -66,9 +65,8 @@ define <8 x i16> @test4(<8 x i16> %A, <8 x i16> %B) {
 ; SSE2-NEXT:    retq
 ; AVX-LABEL: test4:
 ; AVX:       # BB#0
-; AVX-NEXT:    vmovd  %xmm1, %eax
-; AVX-NEXT:    movzwl  %ax, %eax
-; AVX-NEXT:    vmovd  %eax, %xmm1
+; AVX-NEXT:    vpxor  %xmm2, %xmm2, %xmm2
+; AVX-NEXT:    vpblendw  {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
 ; AVX-NEXT:    vpsrlw  %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    retq
 entry:
@@ -121,9 +119,8 @@ define <8 x i16> @test7(<8 x i16> %A, <8 x i16> %B) {
 ; SSE2-NEXT:    retq
 ; AVX-LABEL: test7:
 ; AVX:       # BB#0
-; AVX-NEXT:    vmovd  %xmm1, %eax
-; AVX-NEXT:    movzwl  %ax, %eax
-; AVX-NEXT:    vmovd  %eax, %xmm1
+; AVX-NEXT:    vpxor  %xmm2, %xmm2, %xmm2
+; AVX-NEXT:    vpblendw  {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
 ; AVX-NEXT:    vpsraw  %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    retq
 entry: