now that generic vector types aren't selected onto MMX registers, these

[oota-llvm.git] / test / CodeGen / X86 / inline-asm-mrv.ll

diff --git a/test/CodeGen/X86/inline-asm-mrv.ll b/test/CodeGen/X86/inline-asm-mrv.ll
index 1d83a16ef21006100cddfe2432c3a53e1dc2ad30..78d7e776cf227930191a5a915997f2f20efb5fe4 100644 (file)
--- a/test/CodeGen/X86/inline-asm-mrv.ll
+++ b/test/CodeGen/X86/inline-asm-mrv.ll
@@ -1,12 +1,13 @@
 ; PR2094
-; RUN: llvm-as < %s | llc -march=x86-64 | grep movslq
-; RUN: llvm-as < %s | llc -march=x86-64 | not grep movq
+; RUN: llc < %s -march=x86-64 | grep movslq
+; RUN: llc < %s -march=x86-64 | grep addps
+; RUN: llc < %s -march=x86-64 | grep paddd
+; RUN: llc < %s -march=x86-64 | not grep movq
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-apple-darwin8"
 
-define i32 @sad16_sse2(i8* %v, i8* %blk2, i8* %blk1, i32 %stride, i32 %h) nounwind  {
-entry:
+define i32 @test1(i8* %v, i8* %blk2, i8* %blk1, i32 %stride, i32 %h) nounwind  {
        %tmp12 = sext i32 %stride to i64                ; <i64> [#uses=1]
        %mrv = call {i32, i8*, i8*} asm sideeffect "$0 $1 $2 $3 $4 $5 $6",
          "=r,=r,=r,r,r,r,r"( i64 %tmp12, i32 %h, i8* %blk1, i8* %blk2 ) nounwind
@@ -15,3 +16,20 @@ entry:
              "=r,~{dirflag},~{fpsr},~{flags}"( ) nounwind
        ret i32 %tmp7
 }
+
+define <4 x float> @test2() nounwind {
+       %mrv = call {<4 x float>, <4 x float>} asm "set $0, $1", "=x,=x"()
+       %a = getresult {<4 x float>, <4 x float>} %mrv, 0
+       %b = getresult {<4 x float>, <4 x float>} %mrv, 1
+       %c = fadd <4 x float> %a, %b
+       ret <4 x float> %c
+}
+
+define <4 x i32> @test3() nounwind {
+       %mrv = call {<4 x i32>, <4 x i32>} asm "set $0, $1", "=x,=x"()
+       %a = getresult {<4 x i32>, <4 x i32>} %mrv, 0
+       %b = getresult {<4 x i32>, <4 x i32>} %mrv, 1
+       %c = add <4 x i32> %a, %b
+       ret <4 x i32> %c
+}
+