-; RUN: llc -march=x86 < %s -verify-machineinstrs
-; RUN: llc -march=x86-64 < %s -verify-machineinstrs
-
+; REQUIRES: asserts
+; RUN: llc -march=x86 -no-integrated-as < %s -verify-machineinstrs -precompute-phys-liveness
+; RUN: llc -march=x86-64 -no-integrated-as < %s -verify-machineinstrs -precompute-phys-liveness
+
; PR6497
; Chain and flag folding issues.
ret void
}
-!0 = metadata !{i32 633550}
-!1 = metadata !{i32 634261}
+!0 = metadata !{i32 633550}
+!1 = metadata !{i32 634261}
; Crash during XOR optimization.
; <rdar://problem/9187792>
define fastcc void @func_61() nounwind sspreq {
entry:
- %t1 = tail call i64 @llvm.objectsize.i64(i8* undef, i1 false)
+ %t1 = tail call i64 @llvm.objectsize.i64.p0i8(i8* undef, i1 false)
%t2 = icmp eq i64 %t1, -1
br i1 %t2, label %bb2, label %bb1
ret void
}
-declare i64 @llvm.objectsize.i64(i8*, i1) nounwind readnone
+declare i64 @llvm.objectsize.i64.p0i8(i8*, i1) nounwind readnone
; PR10277
; This test has dead code elimination caused by remat during spilling.
define void @_ZNK4llvm17MipsFrameLowering12emitPrologueERNS_15MachineFunctionE() ssp align 2 {
bb:
- %tmp = load %t9** undef, align 4, !tbaa !0
+ %tmp = load %t9** undef, align 4
%tmp2 = getelementptr inbounds %t9* %tmp, i32 0, i32 0
%tmp3 = getelementptr inbounds %t9* %tmp, i32 0, i32 0, i32 0, i32 0, i32 1
br label %bb4
; uitofp expands to an FCMOV instruction which splits the basic block.
; Make sure the live range of %AL isn't split.
@.str = private unnamed_addr constant { [1 x i8], [63 x i8] } zeroinitializer, align 32
-define void @pr13188(i64* nocapture %this) uwtable ssp address_safety align 2 {
+define void @pr13188(i64* nocapture %this) uwtable ssp sanitize_address align 2 {
entry:
%x7 = load i64* %this, align 8
%sub = add i64 %x7, -1
bb29: ; preds = %bb28, %bb26, %bb25, %bb21
unreachable
}
+
+define void @pr14194() nounwind uwtable {
+ %tmp = load i64* undef, align 16
+ %tmp1 = trunc i64 %tmp to i32
+ %tmp2 = lshr i64 %tmp, 32
+ %tmp3 = trunc i64 %tmp2 to i32
+ %tmp4 = call { i32, i32 } asm sideeffect "", "=&r,=&r,r,r,0,1,~{dirflag},~{fpsr},~{flags}"(i32 %tmp3, i32 undef, i32 %tmp3, i32 %tmp1) nounwind
+ ret void
+}