[X86][SSE] Added full set of 128-bit vector shift tests.

[oota-llvm.git] / test / CodeGen / X86 / convert-2-addr-3-addr-inc64.ll

diff --git a/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll b/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll
index 8e38fe309f7c5e0b1a57c9f67eb5f9b4d01980e4..7fc56f5accc28bd9c00ea25937e4812b82c0010c 100644 (file)
--- a/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll
+++ b/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll
@@ -1,13 +1,18 @@
-; RUN: llc < %s -march=x86-64 -o %t -stats -info-output-file - | \
-; RUN:   grep {asm-printer} | grep {Number of machine instrs printed} | grep 10
-; RUN: grep {leal      1(\%rsi),} %t
+; REQUIRES: asserts
+; RUN: llc < %s -mtriple=x86_64-linux -o /dev/null -stats 2>&1 | FileCheck %s -check-prefix=STATS
+; RUN: llc < %s -mtriple=x86_64-win32 -o /dev/null -stats 2>&1 | FileCheck %s -check-prefix=STATS
+; STATS: 9 asm-printer
+
+; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s
+; CHECK: leal 1({{%rsi|%rdx}}),
 
 define fastcc zeroext i8 @fullGtU(i32 %i1, i32 %i2, i8* %ptr) nounwind optsize {
 entry:
   %0 = add i32 %i2, 1           ; <i32> [#uses=1]
   %1 = sext i32 %0 to i64               ; <i64> [#uses=1]
-  %2 = getelementptr i8* %ptr, i64 %1           ; <i8*> [#uses=1]
-  %3 = load i8* %2, align 1             ; <i8> [#uses=1]
+  %2 = getelementptr i8, i8* %ptr, i64 %1           ; <i8*> [#uses=1]
+  %3 = load i8, i8* %2, align 1             ; <i8> [#uses=1]
   %4 = icmp eq i8 0, %3         ; <i1> [#uses=1]
   br i1 %4, label %bb3, label %bb34