fix invalid load folding with SSE/AVX FP logical instructions (PR22371)

[oota-llvm.git] / test / CodeGen / X86 / commute-clmul.ll

diff --git a/test/CodeGen/X86/commute-clmul.ll b/test/CodeGen/X86/commute-clmul.ll
index fe3e5569bd27339498674c342743e660a26588c8..d13911abc864fe3ced6f40d3095a55845ced4a39 100644 (file)
--- a/test/CodeGen/X86/commute-clmul.ll
+++ b/test/CodeGen/X86/commute-clmul.ll
@@ -12,7 +12,7 @@ define <2 x i64> @commute_lq_lq(<2 x i64>* %a0, <2 x i64> %a1) #0 {
   ;AVX:       vpclmulqdq $0, (%rdi), %xmm0, %xmm0
   ;AVX-NEXT:  retq
 
-  %1 = load <2 x i64>* %a0
+  %1 = load <2 x i64>, <2 x i64>* %a0
   %2 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %a1, i8 0)
   ret <2 x i64> %2
 }
@@ -26,7 +26,7 @@ define <2 x i64> @commute_lq_hq(<2 x i64>* %a0, <2 x i64> %a1) #0 {
   ;AVX:       vpclmulqdq $1, (%rdi), %xmm0, %xmm0
   ;AVX-NEXT:  retq
 
-  %1 = load <2 x i64>* %a0
+  %1 = load <2 x i64>, <2 x i64>* %a0
   %2 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %a1, i8 16)
   ret <2 x i64> %2
 }
@@ -40,7 +40,7 @@ define <2 x i64> @commute_hq_lq(<2 x i64>* %a0, <2 x i64> %a1) #0 {
   ;AVX:       vpclmulqdq $16, (%rdi), %xmm0, %xmm0
   ;AVX-NEXT:  retq
 
-  %1 = load <2 x i64>* %a0
+  %1 = load <2 x i64>, <2 x i64>* %a0
   %2 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %a1, i8 1)
   ret <2 x i64> %2
 }
@@ -54,7 +54,7 @@ define <2 x i64> @commute_hq_hq(<2 x i64>* %a0, <2 x i64> %a1) #0 {
   ;AVX:       vpclmulqdq $17, (%rdi), %xmm0, %xmm0
   ;AVX-NEXT:  retq
 
-  %1 = load <2 x i64>* %a0
+  %1 = load <2 x i64>, <2 x i64>* %a0
   %2 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %a1, i8 17)
   ret <2 x i64> %2
 }