Fix a broadcast related regression on the vector shuffle lowering.

[oota-llvm.git] / test / CodeGen / X86 / cmp.ll

diff --git a/test/CodeGen/X86/cmp.ll b/test/CodeGen/X86/cmp.ll
index 551d9bc6074baf08e6633ba5d60003087c9a0224..149d53759fe2a233d03d037468e26d46998ee351 100644 (file)
--- a/test/CodeGen/X86/cmp.ll
+++ b/test/CodeGen/X86/cmp.ll
@@ -26,9 +26,22 @@ cond_true:           ; preds = %0
 ReturnBlock:           ; preds = %0
        ret i32 0
 ; CHECK-LABEL: test2:
-; CHECK: movl  (%rsi), %eax
-; CHECK: shll  $3, %eax
-; CHECK: testl %eax, %eax
+; CHECK: testl $536870911, (%rsi)
+}
+
+define i8 @test2b(i8 %X, i8* %y) nounwind {
+       %tmp = load i8* %y              ; <i8> [#uses=1]
+       %tmp1 = shl i8 %tmp, 3          ; <i8> [#uses=1]
+       %tmp1.upgrd.2 = icmp eq i8 %tmp1, 0             ; <i1> [#uses=1]
+       br i1 %tmp1.upgrd.2, label %ReturnBlock, label %cond_true
+
+cond_true:             ; preds = %0
+       ret i8 1
+
+ReturnBlock:           ; preds = %0
+       ret i8 0
+; CHECK-LABEL: test2b:
+; CHECK: testb $31, (%rsi)
 }
 
 define i64 @test3(i64 %x) nounwind {
@@ -68,8 +81,8 @@ define i32 @test5(double %A) nounwind  {
  bb12:; preds = %entry
  ret i32 32
 ; CHECK-LABEL: test5:
-; CHECK: ucomisd       LCPI4_0(%rip), %xmm0
-; CHECK: ucomisd       LCPI4_1(%rip), %xmm0
+; CHECK: ucomisd       LCPI5_0(%rip), %xmm0
+; CHECK: ucomisd       LCPI5_1(%rip), %xmm0
 }
 
 declare i32 @foo(...)
@@ -163,3 +176,38 @@ define i32 @test12() uwtable ssp {
 }
 
 declare zeroext i1 @test12b()
+
+define i32 @test13(i32 %mask, i32 %base, i32 %intra) {
+  %and = and i32 %mask, 8
+  %tobool = icmp ne i32 %and, 0
+  %cond = select i1 %tobool, i32 %intra, i32 %base
+  ret i32 %cond
+
+; CHECK-LABEL: test13:
+; CHECK: testb $8, %dil
+; CHECK: cmovnel
+}
+
+define i32 @test14(i32 %mask, i32 %base, i32 %intra) #0 {
+  %s = lshr i32 %mask, 7
+  %tobool = icmp sgt i32 %s, -1
+  %cond = select i1 %tobool, i32 %intra, i32 %base
+  ret i32 %cond
+
+; CHECK-LABEL: test14:
+; CHECK:       shrl    $7, %edi
+; CHECK-NEXT:  cmovnsl %edx, %esi
+}
+
+; PR19964
+define zeroext i1 @test15(i32 %bf.load, i32 %n) {
+  %bf.lshr = lshr i32 %bf.load, 16
+  %cmp2 = icmp eq i32 %bf.lshr, 0
+  %cmp5 = icmp uge i32 %bf.lshr, %n
+  %.cmp5 = or i1 %cmp2, %cmp5
+  ret i1 %.cmp5
+
+; CHECK-LABEL: test15:
+; CHECK:  shrl $16, %edi
+; CHECK:  cmpl %esi, %edi
+}