[X86][SSE] Added full set of 128-bit vector shift tests.

[oota-llvm.git] / test / CodeGen / X86 / avx2-shift.ll

diff --git a/test/CodeGen/X86/avx2-shift.ll b/test/CodeGen/X86/avx2-shift.ll
index 1f192a0d323c22268f4e3d0d4c44dd46f152944f..5adbb2ef6651578f5ecd7b510f66e87321b701fd 100644 (file)
--- a/test/CodeGen/X86/avx2-shift.ll
+++ b/test/CodeGen/X86/avx2-shift.ll
@@ -130,7 +130,7 @@ define <16 x i16> @vshift07(<16 x i16> %a) nounwind readnone {
 ; CHECK: vpsravd (%
 ; CHECK: ret
 define <4 x i32> @variable_sra0_load(<4 x i32> %x, <4 x i32>* %y) {
-  %y1 = load <4 x i32>* %y
+  %y1 = load <4 x i32>, <4 x i32>* %y
   %k = ashr <4 x i32> %x, %y1
   ret <4 x i32> %k
 }
@@ -139,7 +139,7 @@ define <4 x i32> @variable_sra0_load(<4 x i32> %x, <4 x i32>* %y) {
 ; CHECK: vpsravd (%
 ; CHECK: ret
 define <8 x i32> @variable_sra1_load(<8 x i32> %x, <8 x i32>* %y) {
-  %y1 = load <8 x i32>* %y
+  %y1 = load <8 x i32>, <8 x i32>* %y
   %k = ashr <8 x i32> %x, %y1
   ret <8 x i32> %k
 }
@@ -148,7 +148,7 @@ define <8 x i32> @variable_sra1_load(<8 x i32> %x, <8 x i32>* %y) {
 ; CHECK: vpsllvd (%
 ; CHECK: ret
 define <4 x i32> @variable_shl0_load(<4 x i32> %x, <4 x i32>* %y) {
-  %y1 = load <4 x i32>* %y
+  %y1 = load <4 x i32>, <4 x i32>* %y
   %k = shl <4 x i32> %x, %y1
   ret <4 x i32> %k
 }
@@ -156,7 +156,7 @@ define <4 x i32> @variable_shl0_load(<4 x i32> %x, <4 x i32>* %y) {
 ; CHECK: vpsllvd (%
 ; CHECK: ret
 define <8 x i32> @variable_shl1_load(<8 x i32> %x, <8 x i32>* %y) {
-  %y1 = load <8 x i32>* %y
+  %y1 = load <8 x i32>, <8 x i32>* %y
   %k = shl <8 x i32> %x, %y1
   ret <8 x i32> %k
 }
@@ -164,7 +164,7 @@ define <8 x i32> @variable_shl1_load(<8 x i32> %x, <8 x i32>* %y) {
 ; CHECK: vpsllvq (%
 ; CHECK: ret
 define <2 x i64> @variable_shl2_load(<2 x i64> %x, <2 x i64>* %y) {
-  %y1 = load <2 x i64>* %y
+  %y1 = load <2 x i64>, <2 x i64>* %y
   %k = shl <2 x i64> %x, %y1
   ret <2 x i64> %k
 }
@@ -172,7 +172,7 @@ define <2 x i64> @variable_shl2_load(<2 x i64> %x, <2 x i64>* %y) {
 ; CHECK: vpsllvq (%
 ; CHECK: ret
 define <4 x i64> @variable_shl3_load(<4 x i64> %x, <4 x i64>* %y) {
-  %y1 = load <4 x i64>* %y
+  %y1 = load <4 x i64>, <4 x i64>* %y
   %k = shl <4 x i64> %x, %y1
   ret <4 x i64> %k
 }
@@ -180,7 +180,7 @@ define <4 x i64> @variable_shl3_load(<4 x i64> %x, <4 x i64>* %y) {
 ; CHECK: vpsrlvd (%
 ; CHECK: ret
 define <4 x i32> @variable_srl0_load(<4 x i32> %x, <4 x i32>* %y) {
-  %y1 = load <4 x i32>* %y
+  %y1 = load <4 x i32>, <4 x i32>* %y
   %k = lshr <4 x i32> %x, %y1
   ret <4 x i32> %k
 }
@@ -188,7 +188,7 @@ define <4 x i32> @variable_srl0_load(<4 x i32> %x, <4 x i32>* %y) {
 ; CHECK: vpsrlvd (%
 ; CHECK: ret
 define <8 x i32> @variable_srl1_load(<8 x i32> %x, <8 x i32>* %y) {
-  %y1 = load <8 x i32>* %y
+  %y1 = load <8 x i32>, <8 x i32>* %y
   %k = lshr <8 x i32> %x, %y1
   ret <8 x i32> %k
 }
@@ -196,7 +196,7 @@ define <8 x i32> @variable_srl1_load(<8 x i32> %x, <8 x i32>* %y) {
 ; CHECK: vpsrlvq (%
 ; CHECK: ret
 define <2 x i64> @variable_srl2_load(<2 x i64> %x, <2 x i64>* %y) {
-  %y1 = load <2 x i64>* %y
+  %y1 = load <2 x i64>, <2 x i64>* %y
   %k = lshr <2 x i64> %x, %y1
   ret <2 x i64> %k
 }
@@ -204,7 +204,7 @@ define <2 x i64> @variable_srl2_load(<2 x i64> %x, <2 x i64>* %y) {
 ; CHECK: vpsrlvq (%
 ; CHECK: ret
 define <4 x i64> @variable_srl3_load(<4 x i64> %x, <4 x i64>* %y) {
-  %y1 = load <4 x i64>* %y
+  %y1 = load <4 x i64>, <4 x i64>* %y
   %k = lshr <4 x i64> %x, %y1
   ret <4 x i64> %k
 }
@@ -212,7 +212,7 @@ define <4 x i64> @variable_srl3_load(<4 x i64> %x, <4 x i64>* %y) {
 define <32 x i8> @shl9(<32 x i8> %A) nounwind {
   %B = shl <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
   ret <32 x i8> %B
-; CHECK: shl9:
+; CHECK-LABEL: shl9:
 ; CHECK: vpsllw $3
 ; CHECK: vpand
 ; CHECK: ret
@@ -221,7 +221,7 @@ define <32 x i8> @shl9(<32 x i8> %A) nounwind {
 define <32 x i8> @shr9(<32 x i8> %A) nounwind {
   %B = lshr <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
   ret <32 x i8> %B
-; CHECK: shr9:
+; CHECK-LABEL: shr9:
 ; CHECK: vpsrlw $3
 ; CHECK: vpand
 ; CHECK: ret
@@ -230,7 +230,7 @@ define <32 x i8> @shr9(<32 x i8> %A) nounwind {
 define <32 x i8> @sra_v32i8_7(<32 x i8> %A) nounwind {
   %B = ashr <32 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
   ret <32 x i8> %B
-; CHECK: sra_v32i8_7:
+; CHECK-LABEL: sra_v32i8_7:
 ; CHECK: vpxor
 ; CHECK: vpcmpgtb
 ; CHECK: ret
@@ -239,7 +239,7 @@ define <32 x i8> @sra_v32i8_7(<32 x i8> %A) nounwind {
 define <32 x i8> @sra_v32i8(<32 x i8> %A) nounwind {
   %B = ashr <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
   ret <32 x i8> %B
-; CHECK: sra_v32i8:
+; CHECK-LABEL: sra_v32i8:
 ; CHECK: vpsrlw $3
 ; CHECK: vpand
 ; CHECK: vpxor
@@ -266,3 +266,36 @@ define <8 x i32> @sext_v8i32(<8 x i32> %a) nounwind {
   %c = sext <8 x i16> %b to <8 x i32>
   ret <8 x i32> %c
 }
+
+define <8 x i16> @variable_shl16(<8 x i16> %lhs, <8  x i16> %rhs) {
+; CHECK-LABEL: variable_shl16:
+; CHECK-DAG: vpmovzxwd %xmm1, [[AMT:%ymm[0-9]+]]
+; CHECK-DAG: vpmovzxwd %xmm0, [[LHS:%ymm[0-9]+]]
+; CHECK: vpsllvd [[AMT]], [[LHS]], {{%ymm[0-9]+}}
+; CHECK: vpshufb
+; CHECK: vpermq
+  %res = shl <8 x i16> %lhs, %rhs
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @variable_ashr16(<8 x i16> %lhs, <8  x i16> %rhs) {
+; CHECK-LABEL: variable_ashr16:
+; CHECK-DAG: vpmovzxwd %xmm1, [[AMT:%ymm[0-9]+]]
+; CHECK-DAG: vpmovsxwd %xmm0, [[LHS:%ymm[0-9]+]]
+; CHECK: vpsravd [[AMT]], [[LHS]], {{%ymm[0-9]+}}
+; CHECK: vpshufb
+; CHECK: vpermq
+  %res = ashr <8 x i16> %lhs, %rhs
+  ret <8 x i16> %res
+}
+
+define <8 x i16> @variable_lshr16(<8 x i16> %lhs, <8  x i16> %rhs) {
+; CHECK-LABEL: variable_lshr16:
+; CHECK-DAG: vpmovzxwd %xmm1, [[AMT:%ymm[0-9]+]]
+; CHECK-DAG: vpmovzxwd %xmm0, [[LHS:%ymm[0-9]+]]
+; CHECK: vpsrlvd [[AMT]], [[LHS]], {{%ymm[0-9]+}}
+; CHECK: vpshufb
+; CHECK: vpermq
+  %res = lshr <8 x i16> %lhs, %rhs
+  ret <8 x i16> %res
+}
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