Stop producing .data.rel sections.

[oota-llvm.git] / test / CodeGen / X86 / avx2-logic.ll

diff --git a/test/CodeGen/X86/avx2-logic.ll b/test/CodeGen/X86/avx2-logic.ll
index aa3d37d553316c96f6915a52797a659411a92dce..3d4fcec6078ee608480ab2c27fcb8cb5012611f8 100644 (file)
--- a/test/CodeGen/X86/avx2-logic.ll
+++ b/test/CodeGen/X86/avx2-logic.ll
@@ -48,15 +48,14 @@ entry:
 ; CHECK: vpblendvb
 ; CHECK: vpblendvb %ymm
 ; CHECK: ret
-define <32 x i8> @vpblendvb(<32 x i8> %x, <32 x i8> %y) {
-  %min_is_x = icmp ult <32 x i8> %x, %y
-  %min = select <32 x i1> %min_is_x, <32 x i8> %x, <32 x i8> %y
+define <32 x i8> @vpblendvb(<32 x i1> %cond, <32 x i8> %x, <32 x i8> %y) {
+  %min = select <32 x i1> %cond, <32 x i8> %x, <32 x i8> %y
   ret <32 x i8> %min
 }
 
 define <8 x i32> @signd(<8 x i32> %a, <8 x i32> %b) nounwind {
 entry:
-; CHECK: signd:
+; CHECK-LABEL: signd:
 ; CHECK: psignd
 ; CHECK-NOT: sub
 ; CHECK: ret
@@ -71,7 +70,7 @@ entry:
 
 define <8 x i32> @blendvb(<8 x i32> %b, <8 x i32> %a, <8 x i32> %c) nounwind {
 entry:
-; CHECK: blendvb:
+; CHECK-LABEL: blendvb:
 ; CHECK: pblendvb
 ; CHECK: ret
   %b.lobit = ashr <8 x i32> %b, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
@@ -82,3 +81,15 @@ entry:
   %cond = or <8 x i32> %1, %2
   ret <8 x i32> %cond
 }
+
+define <8 x i32> @allOnes() nounwind {
+; CHECK: vpcmpeqd
+; CHECK-NOT: vinsert
+        ret <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
+}
+
+define <16 x i16> @allOnes2() nounwind {
+; CHECK: vpcmpeqd
+; CHECK-NOT: vinsert
+        ret <16 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+}